Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11894359 | Distributed semiconductor die and package architecture | Mark Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley McCullough | 2024-02-06 |
| 11830829 | Device, system and method for providing inductor structures | Mark Bohr, Doug B. Ingerly, Rajesh Kumar, Harish Krishnamurthy, Nachiket Desai | 2023-11-28 |
| 11824041 | Hyperchip | Mark Bohr, Rajesh Kumar, Pooya Tadayon, Doug B. Ingerly | 2023-11-21 |
| 11817442 | Hybrid manufacturing for integrated circuit devices and assemblies | Abhishek A. Sharma, Mauro J. Kobrinsky, Doug B. Ingerly | 2023-11-14 |
| 11756886 | Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures | Abhishek A. Sharma, Mauro J. Kobrinsky, Doug B. Ingerly | 2023-09-12 |
| 11749663 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Mark Bohr, Glenn J. Hinton, Rajesh Kumar | 2023-09-05 |
| 11690211 | Thin film transistor based memory cells on both sides of a layer of logic devices | Mauro J. Kobrinsky, Conor P. Puls, Kevin J. Fischer, Bernhard Sell, Abhishek A. Sharma +1 more | 2023-06-27 |
| 11652060 | Die interconnection scheme for providing a high yielding process for high performance microprocessors | Mark Bohr, Rajabali M. Koduri, Leonard NEIBERG, Altug Koker, Swaminathan Sivakumar | 2023-05-16 |
| 11569173 | Bridge hub tiling architecture | Andrew Collins, Digvijay A. Raorane, Ravindranath V. Mahajan, Sujit Sharan | 2023-01-31 |
| 11387198 | Device, system and method for providing inductor structures | Mark Bohr, Doug B. Ingerly, Rajesh Kumar, Harish Krishnamurthy, Nachiket Desai | 2022-07-12 |
| 11373987 | Device, method and system for providing a stacked arrangement of integrated circuit dies | Mark Bohr, Glenn J. Hinton, Rajesh Kumar | 2022-06-28 |
| 11335686 | Transistors with back-side contacts to create three dimensional memory and logic | Mauro J. Kobrinsky, Abhishek A. Sharma, Tahir Ghani, Doug B. Ingerly, Rajesh Kumar | 2022-05-17 |
| 11257822 | Three-dimensional nanoribbon-based dynamic random-access memory | Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar | 2022-02-22 |
| 11257804 | Distributed semiconductor die and package architecture | Mark Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2022-02-22 |
| 11239238 | Thin film transistor based memory cells on both sides of a layer of logic devices | Mauro J. Kobrinsky, Conor P. Puls, Kevin J. Fischer, Bernhard Sell, Abhishek A. Sharma +1 more | 2022-02-01 |
| 11139300 | Three-dimensional memory arrays with layer selector transistors | Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot N. Tan +2 more | 2021-10-05 |
| 11127712 | Functionally redundant semiconductor dies and package | Mark Bohr, Udi Sherel, Leonard NEIBERG, Nevine Nassif, Wesley McCullough | 2021-09-21 |
| 11087832 | Three-dimensional nanoribbon-based static random-access memory | Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani | 2021-08-10 |
| 11056492 | Dense memory arrays utilizing access transistors with back-side contacts | Mauro J. Kobrinsky, Elliot N. Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar +1 more | 2021-07-06 |
| 11024601 | Hyperchip | Mark Bohr, Rajesh Kumar, Pooya Tadayon, Doug B. Ingerly | 2021-06-01 |
| 11018264 | Three-dimensional nanoribbon-based logic | Kinyip Phoa, Tahir Ghani, Rajesh Kumar | 2021-05-25 |
| 10784204 | Rlink—die to die channel interconnect configurations to improve signaling | Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Yu Zhang +7 more | 2020-09-22 |
| 10685947 | Distributed semiconductor die and package architecture | Mark Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough | 2020-06-16 |