Issued Patents All Time
Showing 376–400 of 534 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7893529 | Thermoelectric 3D cooling | Louis L. Hsu, Ping-Chuan Wang, Xiaojin Wei | 2011-02-22 |
| 7883976 | Structure and method for manufacturing device with planar halo profile | Jing Wang | 2011-02-08 |
| 7883956 | Method of forming coplanar active and isolation regions and structures thereof | — | 2011-02-08 |
| 7883944 | Ultra-thin semiconductor on insulator metal gate complementary field effect transistor with metal gate and method of forming thereof | Bruce B. Doris, Philip J. Oldiges | 2011-02-08 |
| 7880238 | 2-T SRAM cell structure and method | Qingqing Liang, Werner Rausch | 2011-02-01 |
| 7863169 | Lithography for printing constant line width features | — | 2011-01-04 |
| 7863143 | High performance schottky-barrier-source asymmetric MOSFETs | Qingqing Liang, Gregory G. Freeman | 2011-01-04 |
| 7858485 | Structure and method for manufacturing trench capacitance | Babar A. Khan, Xi Li, Joyce C. Liu, Thomas A. Wallner | 2010-12-28 |
| 7838913 | Hybrid FET incorporating a finFET and a planar FET | Kangguo Cheng, Qingqing Liang | 2010-11-23 |
| 7829939 | MOSFET including epitaxial halo region | Qingqing Liang, Jing Wang | 2010-11-09 |
| 7824989 | Method for reducing overlap capacitance in field effect transistors | Oleg Gluschenkov | 2010-11-02 |
| 7824969 | Finfet devices and methods for manufacturing the same | — | 2010-11-02 |
| 7816760 | Semiconductor structure including laminated isolation region | Zhijiong Luo | 2010-10-19 |
| 7816261 | MOSFETS comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same | Hong Lin | 2010-10-19 |
| 7816219 | Field effect transistors (FETs) with multiple and/or staircase silicide | Xiangdong Chen, Sunfei Fang, Zhijiong Luo, Haining Yang | 2010-10-19 |
| 7813162 | SRAM cell having asymmetric pass gates | Qingqing Liang | 2010-10-12 |
| 7800152 | Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom | Bruce B. Doris | 2010-09-21 |
| 7791112 | Channel stress engineering using localized ion implantation induced gate electrode volumetric change | Zhjiong Luo | 2010-09-07 |
| 7790581 | Semiconductor substrate with multiple crystallographic orientations | Byeong Y. Kim, Xiaomeng Chen, Woo-Hyeong Lee | 2010-09-07 |
| 7790558 | Method and apparatus for increase strain effect in a transistor channel | Haining Yang | 2010-09-07 |
| 7790553 | Methods for forming high performance gates and structures thereof | Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay William Strane +1 more | 2010-09-07 |
| 7785944 | Method of making double-gated self-aligned finFET having gates of different lengths | Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges | 2010-08-31 |
| 7785943 | Method for forming a multi-gate device with high k dielectric for channel top surface | Bruce B. Doris, Oleg Gluschenkov, Ying Zhang | 2010-08-31 |
| 7781278 | CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same | — | 2010-08-24 |
| 7781273 | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure | Dominic J. Schepis | 2010-08-24 |