Issued Patents All Time
Showing 951–975 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9601335 | Trench formation for dielectric filled cut region | Andrew M. Greene, Ryan O. Jung, Peng Xu | 2017-03-21 |
| 9601366 | Trench formation for dielectric filled cut region | Andrew M. Greene, Ryan O. Jung, Peng Xu | 2017-03-21 |
| 9589833 | Preventing leakage inside air-gap spacer during contact formation | Kangguo Cheng, Tenko Yamashita | 2017-03-07 |
| 9589847 | Metal layer tip to tip short | Cheng Chi | 2017-03-07 |
| 9583597 | Asymmetric FinFET semiconductor devices and methods for fabricating the same | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2017-02-28 |
| 9576956 | Method and structure of forming controllable unmerged epitaxial material | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2017-02-21 |
| 9576954 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Balasubramanian Pranatharthiharan | 2017-02-21 |
| 9576857 | Method and structure for SRB elastic relaxation | Murat Kerem Akarvardar, Andreas Knorr | 2017-02-21 |
| 9570573 | Self-aligned gate tie-down contacts with selective etch stop liner | Su Chen Fan, Lars Liebmann | 2017-02-14 |
| 9570583 | Recessing RMG metal gate stack for forming self-aligned contact | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2017-02-14 |
| 9570397 | Local interconnect structure including non-eroded contact via trenches | Su Chen Fan, Vimal Kamineni, Andre P. Labonte | 2017-02-14 |
| 9570555 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Balasubramanian Pranatharthiharan, Junli Wang | 2017-02-14 |
| 9564358 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2017-02-07 |
| 9564372 | Dual liner silicide | Balasubramanian Pranatharthiharan, Chun-Chen Yeh | 2017-02-07 |
| 9564501 | Reduced trench profile for a gate | Qing Liu, Xiuyu Cai, Chun-Chen Yeh | 2017-02-07 |
| 9559018 | Dual channel finFET with relaxed pFET region | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2017-01-31 |
| 9558995 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan | 2017-01-31 |
| 9559009 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert | 2017-01-31 |
| 9552992 | Co-fabrication of non-planar semiconductor devices having different threshold voltages | Hoon Kim, Min Gyu Sung, Chanro Park | 2017-01-24 |
| 9553028 | Methods of forming reduced resistance local interconnect structures and the resulting devices | Ryan Ryoung-Han Kim | 2017-01-24 |
| 9548388 | Forming field effect transistor device spacers | Rama Kambhampati, Junli Wang, Tenko Yamashita | 2017-01-17 |
| 9543216 | Integration of hybrid germanium and group III-V contact epilayer in CMOS | Hiroaki Niimi | 2017-01-10 |
| 9543426 | Semiconductor devices with self-aligned contacts and low-k spacers | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2017-01-10 |
| 9536982 | Etch stop for airgap protection | Kangguo Cheng, Tenko Yamashita | 2017-01-03 |
| 9536750 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Cheng Chi, Fee Li Lie, Chi-Chun Liu | 2017-01-03 |