Issued Patents All Time
Showing 901–925 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773881 | Etch stop for airgap protection | Kangguo Cheng, Tenko Yamashita | 2017-09-26 |
| 9761495 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Min Gyu Sung, Catherine B. Labelle, Chanro Park, Hoon Kim | 2017-09-12 |
| 9755031 | Trench epitaxial growth for a FinFET device having reduced capacitance | Qing Liu, Xiuyu Cai, Chun-Chen Yeh | 2017-09-05 |
| 9748351 | Process for integrated circuit fabrication including a uniform depth tungsten recess technique | Qing Liu, Chun-Chen Yeh | 2017-08-29 |
| 9748352 | Multi-channel gate-all-around FET | Qing Liu, Chun-Chen Yeh, Xiuyu Cai | 2017-08-29 |
| 9741623 | Dual liner CMOS integration methods for FinFET devices | Min Gyu Sung, Chanro Park, Hoon Kim | 2017-08-22 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2017-08-22 |
| 9735063 | Methods for forming fin structures | Chanro Park, Min Gyu Sung, Hoon Kim | 2017-08-15 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Min Gyu Sung, Chanro Park, Hoon Kim | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Chanro Park, Min Gyu Sung, Hoon Kim | 2017-08-15 |
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Hoon Kim, Min Gyu Sung, Chanro Park | 2017-08-15 |
| 9722024 | Formation of semiconductor structures employing selective removal of fins | Catherine B. Labelle, Min Gyu Sung | 2017-08-01 |
| 9721834 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan | 2017-08-01 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Hoon Kim, Chanro Park, Sukwon Hong | 2017-08-01 |
| 9716170 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2017-07-25 |
| 9711503 | Gate structures with protected end surfaces to eliminate or reduce unwanted EPI material growth | Shom Ponoth, Juntao Li | 2017-07-18 |
| 9711618 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2017-07-18 |
| 9704973 | Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins | Andy Wei | 2017-07-11 |
| 9698230 | MOSFET with asymmetric self-aligned contact | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2017-07-04 |
| 9698101 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty | 2017-07-04 |
| 9691897 | Three-dimensional semiconductor transistor with gate contact in active region | Andre P. Labonte, Andreas Knorr | 2017-06-27 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Min Gyu Sung, Chanro Park, Hoon Kim | 2017-06-27 |
| 9685555 | High-reliability, low-resistance contacts for nanoscale transistors | Qing Liu, Nicolas Loubet, Chun-Chen Yeh, Xiuyu Cai | 2017-06-20 |
| 9685537 | Gate length control for vertical transistors and integration with replacement gate flow | Tenko Yamashita, Kangguo Cheng, Chun-Chen Yeh | 2017-06-20 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Hoon Kim, Min Gyu Sung, Chanro Park | 2017-06-20 |