Issued Patents All Time
Showing 926–950 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9685384 | Devices and methods of forming epi for aggressive gate pitch | Christopher M. Prindle, Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Pietro Montanini, Shogo Mochizuki | 2017-06-20 |
| 9666791 | Topological method to build self-aligned MTJ without a mask | Xunyuan Zhang, Xiuyu Cai, Seowoo Nam, Hyun-Jin Cho | 2017-05-30 |
| 9660083 | LDMOS finFET device and method of manufacture using a trench confined epitaxial growth process | Qing Liu, Chun-Chen Yeh, Xiuyu Cai | 2017-05-23 |
| 9660057 | Method of forming a reduced resistance fin structure | Qing Liu, Chun-Chen Yeh, Xiuyu Cai, Kejia Wang | 2017-05-23 |
| 9660050 | Replacement low-k spacer | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2017-05-23 |
| 9659786 | Gate cut with high selectivity to preserve interlevel dielectric layer | Andrew M. Greene, Ryan O. Jung | 2017-05-23 |
| 9659785 | Fin cut for taper device | Kangguo Cheng, Tenko Yamashita | 2017-05-23 |
| 9653579 | Method for making semiconductor device with filled gate line end recesses | Qing Liu, Xiuyu Cai, Chun-Chen Yeh, Kejia Wang | 2017-05-16 |
| 9653356 | Methods of forming self-aligned device level contact structures | Chanro Park, Min Gyu Sung, Hoon Kim | 2017-05-16 |
| 9647093 | Fin cut for taper device | Kangguo Cheng, Tenko Yamashita | 2017-05-09 |
| 9646962 | Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET | Qing Liu, Chun-Chen Yeh | 2017-05-09 |
| 9640633 | Self aligned gate shape preventing void formation | Andrew M. Greene, Qing Liu, Chun-Chen Yeh | 2017-05-02 |
| 9640535 | Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices | Hiroaki Niimi | 2017-05-02 |
| 9640436 | MOSFET with asymmetric self-aligned contact | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2017-05-02 |
| 9633906 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert | 2017-04-25 |
| 9634115 | Methods of forming a protection layer on a semiconductor device and the resulting device | Chanro Park, Xiuyu Cai | 2017-04-25 |
| 9634110 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Balasubramanian Pranatharthiharan | 2017-04-25 |
| 9634010 | Field effect transistor device spacers | Rama Kambhampati, Junli Wang, Tenko Yamashita | 2017-04-25 |
| 9634004 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2017-04-25 |
| 9627377 | Self-aligned dielectric isolation for FinFET devices | Marc A. Bergendahl, Kangguo Cheng, David V. Horak, Ali Khakifirooz, Shom Ponoth +4 more | 2017-04-18 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Hoon Kim, Chanro Park, Min Gyu Sung | 2017-04-18 |
| 9620505 | Semiconductor device with different fin sets | Qing Liu, Xiuyu Cai, Chun-Chen Yeh, Kejia Wang, Daniel Chanemougame | 2017-04-11 |
| 9614047 | Gate contact with vertical isolation from source-drain | David V. Horak, Shom Ponoth, Balasubramanian Pranatharthiharan | 2017-04-04 |
| 9614056 | Methods of forming a tri-gate FinFET device | Andreas Knorr | 2017-04-04 |
| 9607903 | Method for forming field effect transistors | Rama Kambhampati, Junli Wang, Tenko Yamashita | 2017-03-28 |