Issued Patents All Time
Showing 876–900 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837276 | Gate cut with high selectivity to preserve interlevel dielectric layer | Andrew M. Greene, Ryan O. Jung | 2017-12-05 |
| 9831132 | Methods for forming fin structures | Chanro Park, Min Gyu Sung, Hoon Kim | 2017-11-28 |
| 9831100 | Solution based etching of titanium carbide and titanium nitride structures | John Foster, Sean Xuan Lin, Muthumanickam Sankarapandian | 2017-11-28 |
| 9824921 | Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps | Andre P. Labonte, Xunyuan Zhang | 2017-11-21 |
| 9824970 | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures | Xunyuan Zhang | 2017-11-21 |
| 9824920 | Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices | Chanro Park, Hoon Kim, Min Gyu Sung | 2017-11-21 |
| 9818823 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2017-11-14 |
| 9818836 | Gate cut method for replacement metal gate integration | Min Gyu Sung, Chanro Park, Dong-Ick Lee | 2017-11-14 |
| 9812443 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2017-11-07 |
| 9812543 | Common metal contact regions having different Schottky barrier heights and methods of manufacturing same | Tek Po Rinus Lee, Jinping Liu | 2017-11-07 |
| 9812365 | Methods of cutting gate structures on transistor devices | John H. Zhang, Haigou Huang, Xusheng Wu, Stan Tsai | 2017-11-07 |
| 9806153 | Controlling channel length for vertical FETs | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2017-10-31 |
| 9806078 | FinFET spacer formation on gate sidewalls, between the channel and source/drain regions | Christopher M. Prindle, Tenko Yamashita, Balasubramanian Pranatharthiharan, Pietro Montanini, Soon-Cheon Seo | 2017-10-31 |
| 9799746 | Preventing leakage inside air-gap spacer during contact formation | Kangguo Cheng, Tenko Yamashita | 2017-10-24 |
| 9799748 | Method of forming inner spacers on a nano-sheet/wire device | Min Gyu Sung, Chanro Park, Hoon Kim | 2017-10-24 |
| 9793157 | Etch stop for airgap protection | Kangguo Cheng, Tenko Yamashita | 2017-10-17 |
| 9793395 | Vertical vacuum channel transistor | Qing Liu, Chun-Chen Yeh | 2017-10-17 |
| 9793171 | Buried source-drain contact for integrated circuit transistor devices and method of making same | Qing Liu, Chun-Chen Yeh, Xiuyu Cai, William J. Taylor, Jr. | 2017-10-17 |
| 9786557 | Two-dimensional self-aligned super via integration on self-aligned gate contact | Cheng Chi | 2017-10-10 |
| 9779960 | Hybrid fin cutting processes for FinFET semiconductor devices | Min Gyu Sung, Catherine B. Labelle | 2017-10-03 |
| 9780178 | Methods of forming a gate contact above an active region of a semiconductor device | Andre P. Labonte, Andreas Knorr | 2017-10-03 |
| 9780197 | Method of controlling VFET channel length | Min Gyu Sung, Chanro Park, Hoon Kim | 2017-10-03 |
| 9780208 | Method and structure of forming self-aligned RMG gate for VFET | Chanro Park, Min Gyu Sung, Hoon Kim | 2017-10-03 |
| 9773867 | FinFET semiconductor devices with replacement gate structures | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2017-09-26 |
| 9773885 | Self aligned gate shape preventing void formation | Andrew M. Greene, Qing Liu, Chun-Chen Yeh | 2017-09-26 |