Issued Patents All Time
Showing 826–850 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9947774 | Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping | Kangguo Cheng, Tenko Yamashita | 2018-04-17 |
| 9941162 | Self-aligned middle of the line (MOL) contacts | Daniel Chanemougame, Lars Liebmann | 2018-04-10 |
| 9941278 | Method and apparatus for placing a gate contact inside an active region of a semiconductor | Andre P. Labonte, Xunyuan Zhang | 2018-04-10 |
| 9935003 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan | 2018-04-03 |
| 9935018 | Methods of forming vertical transistor devices with different effective gate lengths | Chun-Chen Yeh, Tenko Yamashita, Kangguo Cheng | 2018-04-03 |
| 9935180 | Fin cut for taper device | Kangguo Cheng, Tenko Yamashita | 2018-04-03 |
| 9935179 | Method for making semiconductor device with filled gate line end recesses | Xiuyu Cai, Qing Liu, Kejia Wang, Chun-Chen Yeh | 2018-04-03 |
| 9935168 | Gate contact with vertical isolation from source-drain | David V. Horak, Shom Ponoth, Balasubramanian Pranatharthiharan | 2018-04-03 |
| 9935201 | High doped III-V source/drain junctions for field effect transistors | Xiuyu Cai, Qing Liu, Kejia Wang, Chun-Chen Yeh | 2018-04-03 |
| 9929020 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Cheng Chi, Fee Li Lie, Chi-Chun Liu | 2018-03-27 |
| 9929048 | Middle of the line (MOL) contacts with two-dimensional self-alignment | Chanro Park, Andre P. Labonte, Lars Liebmann | 2018-03-27 |
| 9929057 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan | 2018-03-27 |
| 9929059 | Dual liner silicide | Balasubramanian Pranatharthiharan, Chun-Chen Yeh | 2018-03-27 |
| 9929157 | Tall single-fin fin-type field effect transistor structures and methods | Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel G. Cave | 2018-03-27 |
| 9929246 | Forming air-gap spacer for vertical field effect transistor | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-03-27 |
| 9929247 | Etch stop for airgap protection | Kangguo Cheng, Tenko Yamashita | 2018-03-27 |
| 9929253 | Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2018-03-27 |
| 9923078 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Balasubramanian Pranatharthiharan | 2018-03-20 |
| 9923080 | Gate height control and ILD protection | Andrew M. Greene, John R. Sporre, Stan Tsai | 2018-03-20 |
| 9923055 | Inner spacer for nanosheet transistors | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-03-20 |
| 9922883 | Method for making strained semiconductor device and related methods | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2018-03-20 |
| 9917195 | High doped III-V source/drain junctions for field effect transistors | Xiuyu Cai, Qing Liu, Kejia Wang, Chun-Chen Yeh | 2018-03-13 |
| 9917162 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-03-13 |
| 9917152 | Nanosheet transistors on bulk material | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-03-13 |
| 9917081 | Semiconductor device including finFET and fin varactor | Kangguo Cheng, Junli Wang, Tenko Yamashita | 2018-03-13 |