Issued Patents All Time
Showing 51–75 of 209 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12136655 | Backside electrical contacts to buried power rails | Ruilong Xie, Brent A. Anderson, Albert M. Young, Kangguo Cheng, Balasubramanian Pranatharthiharan +2 more | 2024-11-05 |
| 12119341 | Electrostatic discharge diode having dielectric isolation layer | Huimei Zhou, Xuefeng Liu, Jingyun Zhang, Lan Yu, Heng Wu +2 more | 2024-10-15 |
| 12112782 | Compact MRAM architecture with magnetic bottom electrode | Karthik Yogendra, Dimitri Houssameddine, Kangguo Cheng, Ruilong Xie | 2024-10-08 |
| 12106969 | Substrate thinning for a backside power distribution network | Ruilong Xie, Balasubramanian Pranatharthiharan, Mukta G. Farooq, Takeshi Nogami, Roy R. Yu +1 more | 2024-10-01 |
| 12107014 | Nanosheet transistors with self-aligned gate cut | Huimei Zhou, Ruilong Xie, Chanro Park, Kangguo Cheng | 2024-10-01 |
| 12100746 | Gate-all-around field effect transistor with bottom dielectric isolation | Nicolas Loubet, Andrew M. Greene, Ruilong Xie, Maruf Amin Bhuiyan, Veeraraghavan S. Basker | 2024-09-24 |
| 12094972 | Gate-all-around field effect transistors having end portions of nanosheet channel layers adjacent to source/drain regions being wider than the center portions | Ruilong Xie, Kangguo Cheng, Chanro Park | 2024-09-17 |
| 12087770 | Complementary field effect transistor devices | Ruilong Xie, Heng Wu, Chen Zhang, Kangguo Cheng | 2024-09-10 |
| 12087691 | Semiconductor structures with backside gate contacts | Ruilong Xie, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet, Dechao Guo +3 more | 2024-09-10 |
| 12080709 | Dual inner spacer epitaxy in monolithic stacked FETs | Sagarika Mukesh, Nicolas Loubet, Ruilong Xie | 2024-09-03 |
| 12046643 | Semiconductor structures with power rail disposed under active gate | Ruilong Xie, Kangguo Cheng, Chanro Park | 2024-07-23 |
| 12027224 | Authenticity and yield by reading defective cells | Kangguo Cheng, Ruilong Xie | 2024-07-02 |
| 12009435 | Integrated nanosheet field effect transistors and floating gate memory cells | Ruilong Xie, Veeraraghavan S. Basker, Alexander Reznicek | 2024-06-11 |
| 12002850 | Nanosheet-based semiconductor structure with dielectric pillar | Kangguo Cheng, Ruilong Xie, Chanro Park | 2024-06-04 |
| 12002808 | Dual dielectric pillar fork sheet device | Ruilong Xie, Kangguo Cheng, Dimitri Houssameddine | 2024-06-04 |
| 11963456 | MRAM memory array yield improvement | Dimitri Houssameddine, Kangguo Cheng, Ruilong Xie | 2024-04-16 |
| 11961544 | Spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) with low resistivity spin hall effect (SHE) write line | Dimitri Houssameddine, Ruilong Xie, Kangguo Cheng | 2024-04-16 |
| 11955526 | Thick gate oxide device option for nanosheet device | Ruilong Xie, Kangguo Cheng, Chanro Park, Veeraraghavan S. Basker | 2024-04-09 |
| 11948944 | Optimized contact resistance for stacked FET devices | Ruilong Xie, Heng Wu, Jingyun Zhang | 2024-04-02 |
| 11942374 | Nanosheet field effect transistor with a source drain epitaxy replacement | Ruilong Xie, Chanro Park, Kangguo Cheng | 2024-03-26 |
| 11935930 | Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors | Ruilong Xie, Kangguo Cheng, Chanro Park, Andrew Gaul | 2024-03-19 |
| 11935929 | High aspect ratio shared contacts | Ruilong Xie, Su Chen Fan, Ravikumar Ramachandran, Nicolas Loubet | 2024-03-19 |
| 11923363 | Semiconductor structure having bottom isolation and enhanced carrier mobility | Ruilong Xie, Kangguo Cheng, Chanro Park, Juntao Li | 2024-03-05 |
| 11916073 | Stacked complementary field effect transistors | Ruilong Xie, Kangguo Cheng, Chanro Park | 2024-02-27 |
| 11908743 | Planar devices with consistent base dielectric | Huimei Zhou, Andrew M. Greene, Ruqiang Bao, Jingyun Zhang, Miaomiao Wang +1 more | 2024-02-20 |