Issued Patents All Time
Showing 301–325 of 401 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10535517 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Ruqiang Bao, Gen Tsutsui, Dechao Guo | 2020-01-14 |
| 10529573 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Vijay Narayanan | 2020-01-07 |
| 10529850 | Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile | Chun Wing Yeung, Jingyun Zhang, Robin Hsin Kuo Chao, Heng Wu | 2020-01-07 |
| 10529798 | Multiple work function device using GeOx/TiN cap on work function setting metal | Takashi Ando, Pouya Hashemi | 2020-01-07 |
| 10529716 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Jingyun Zhang, Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2020-01-07 |
| 10529628 | Semiconductor device and method of forming the semiconductor device | Brent A. Anderson, Ruqiang Bao, Paul C. Jamison | 2020-01-07 |
| 10529851 | Forming bottom source and drain extension on vertical transport FET (VTFET) | Shogo Mochizuki, Kangguo Cheng, Juntao Li | 2020-01-07 |
| 10522649 | Inverse T-shaped contact structures having air gap spacers | Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu | 2019-12-31 |
| 10522594 | Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element | Peng Xu, Kangguo Cheng, Juntao Li | 2019-12-31 |
| 10522419 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2019-12-31 |
| 10504997 | Silicon-germanium Fin structure having silicon-rich outer surface | Hemanth Jagannathan, Shogo Mochizuki, Koji Watanabe | 2019-12-10 |
| 10504794 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Kangguo Cheng, Juntao Li, Peng Xu | 2019-12-10 |
| 10497796 | Vertical transistor with reduced gate length variation | Kangguo Cheng, Juntao Li, Peng Xu | 2019-12-03 |
| 10497752 | Resistive random-access memory array with reduced switching resistance variability | Takashi Ando, Seyoung Kim, Wilfried E. Haensch | 2019-12-03 |
| 10490559 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions | Takashi Ando, Ruqiang Bao, Pouya Hashemi | 2019-11-26 |
| 10483361 | Wrap-around-contact structure for top source/drain in vertical FETs | Christopher J. Waskiewicz, Alexander Reznicek, Hemanth Jagannathan | 2019-11-19 |
| 10475923 | Method and structure for forming vertical transistors with various gate lengths | Kangguo Cheng, Shogo Mochizuki, Juntao Li | 2019-11-12 |
| 10468532 | Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor | Alexander Reznicek, Xin Miao, Jingyun Zhang | 2019-11-05 |
| 10468498 | Vertical fin bipolar junction transistor with high germanium content silicon germanium base | Seyoung Kim, Injo Ok, Soon-Cheon Seo | 2019-11-05 |
| 10461184 | Transistor having reduced gate-induced drain-leakage current | Kangguo Cheng | 2019-10-29 |
| 10460982 | Formation of semiconductor devices with dual trench isolations | Juntao Li, Kangguo Cheng, Peng Xu | 2019-10-29 |
| 10453940 | Vertical field effect transistor with strained channel region extension | Shogo Mochizuki, Juntao Li, Kangguo Cheng | 2019-10-22 |
| 10453844 | Techniques for enhancing vertical gate-all-around FET performance | Injo Ok, Soon-Cheon Seo, Seyoung Kim | 2019-10-22 |
| 10453937 | Self-limited inner spacer formation for gate-all-around field effect transistors | Robinhsinku Chao, Heng Wu, Chun Wing Yeung, Jingyun Zhang | 2019-10-22 |
| 10446664 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2019-10-15 |