Issued Patents All Time
Showing 326–350 of 401 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439043 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Hemanth Jagannathan, Shogo Mochizuki | 2019-10-08 |
| 10439044 | Method and structure of fabricating I-shaped silicon germanium vertical field-effect transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2019-10-08 |
| 10431502 | Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact | Shogo Mochizuki, Chun Wing Yeung, Hemanth Jagannathan | 2019-10-01 |
| 10431660 | Self-limiting fin spike removal | Kangguo Cheng, Juntao Li, Peng Xu | 2019-10-01 |
| 10424482 | Methods and structures for forming a tight pitch structure | Peng Xu, Kangguo Cheng, Juntao Li | 2019-09-24 |
| 10418288 | Techniques for forming different gate length vertical transistors with dual gate oxide | Ruqiang Bao, Shogo Mochizuki, Chun Wing Yeung | 2019-09-17 |
| 10410928 | Homogeneous densification of fill layers for controlled reveal of vertical fins | Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu | 2019-09-10 |
| 10395994 | Equal spacer formation on semiconductor device | Heng Wu, Juntao Li, Peng Xu, Kangguo Cheng | 2019-08-27 |
| 10396126 | Resistive memory device with electrical gate control | Seyoung Kim, Takashi Ando, Injo Ok, Soon-Cheon Seo | 2019-08-27 |
| 10396151 | Vertical field effect transistor with reduced gate to source/drain capacitance | Juntao Li, Kangguo Cheng, Peng Xu | 2019-08-27 |
| 10395079 | Simplified gate stack process to improve dual channel CMOS performance | Hemanth Jagannathan, Richard Southwick | 2019-08-27 |
| 10395080 | Simplified gate stack process to improve dual channel CMOS performance | Hemanth Jagannathan, Richard Southwick | 2019-08-27 |
| 10395989 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs | Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison | 2019-08-27 |
| 10388766 | Vertical transport FET (VFET) with dual top spacer | Shogo Mochizuki, Michael P. Belyansky | 2019-08-20 |
| 10388755 | Stacked nanosheets with self-aligned inner spacers and metallic source/drain | Kangguo Cheng, Juntao Li | 2019-08-20 |
| 10381438 | Vertically stacked NFETS and PFETS with gate-all-around structure | Jingyun Zhang, Takashi Ando, Pouya Hashemi, Alexander Reznicek | 2019-08-13 |
| 10381074 | Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors | Seyoung Kim, Soon-Cheon Seo, Injo Ok | 2019-08-13 |
| 10373912 | Replacement metal gate processes for vertical transport field-effect transistor | Chun Wing Yeung, Ruqiang Bao, Hemanth Jagannathan | 2019-08-06 |
| 10361125 | Methods and structures for forming uniform fins when using hardmask patterns | Peng Xu, Kangguo Cheng, Yann Mignot | 2019-07-23 |
| 10361237 | Low dark current backside illumination sensor | Takashi Ando | 2019-07-23 |
| 10361131 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2019-07-23 |
| 10361130 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Ruqiang Bao, Hemanth Jagannathan, Richard Southwick | 2019-07-23 |
| 10355103 | Long channels for transistors | Robin Hsin Kuo Chao, Heng Wu, Chun Wing Yeung, Jingyun Zhang | 2019-07-16 |
| 10347456 | Vertical vacuum channel transistor with minimized air gap between tip and gate | Injo Ok, Soon-Cheon Seo, Seyoung Kim | 2019-07-09 |
| 10340363 | Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers | Shogo Mochizuki | 2019-07-02 |