Issued Patents All Time
Showing 376–400 of 401 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10229986 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Alexander Reznicek, Christopher J. Waskiewicz | 2019-03-12 |
| 10229975 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Hemanth Jagannathan, Shogo Mochizuki, Koji Watanabe | 2019-03-12 |
| 10229856 | Dual channel CMOS having common gate stacks | Takashi Ando, Hemanth Jagannathan, Vijay Narayanan | 2019-03-12 |
| 10170577 | Vertical transport FETs having a gradient threshold voltage | Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10157923 | Vertical transport transistors with equal gate stack thicknesses | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2018-12-18 |
| 10147820 | Germanium condensation for replacement metal gate devices with silicon germanium channel | Takashi Ando, Pouya Hashemi | 2018-12-04 |
| 10141232 | Vertical CMOS devices with common gate stacks | Injo Ok, Soon-Cheon Seo | 2018-11-27 |
| 10141420 | Transistors with dielectric-isolated source and drain regions | Kangguo Cheng, Juntao Li, Peng Xu | 2018-11-27 |
| 10134642 | Semiconductor device and method of forming the semiconductor device | Brent A. Anderson, Ruqiang Bao, Paul C. Jamison | 2018-11-20 |
| 10134833 | Multiple work function device using GeOx/TiN cap on work function setting metal | Takashi Ando, Pouya Hashemi | 2018-11-20 |
| 10128372 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Shogo Mochizuki, Hemanth Jagannathan | 2018-11-13 |
| 10115800 | Vertical fin bipolar junction transistor with high germanium content silicon germanium base | Seyoung Kim, Injo Ok, Soon-Cheon Seo | 2018-10-30 |
| 10103147 | Vertical transport transistors with equal gate stack thicknesses | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2018-10-16 |
| 10084082 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Shogo Mochizuki, Hemanth Jagannathan | 2018-09-25 |
| 10084055 | Uniform threshold voltage for nanosheet devices | Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, Vijay Narayanan, Koji Watanabe | 2018-09-25 |
| 10079233 | Semiconductor device and method of forming the semiconductor device | Robin Hsin Kuo Chao, Hemanth Jagannathan, Chun Wing Yeung, Jingyun Zhang | 2018-09-18 |
| 10008386 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Vijay Narayanan | 2018-06-26 |
| 10008417 | Vertical transport fin field effect transistors having different channel lengths | Ruqiang Bao, Shogo Mochizuki, Chun Wing Yeung | 2018-06-26 |
| 10002791 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS | Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison | 2018-06-19 |
| 9984263 | Simplified gate stack process to improve dual channel CMOS performance | Hemanth Jagannathan, Richard Southwick | 2018-05-29 |
| 9960272 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Shogo Mochizuki, Hemanth Jagannathan | 2018-05-01 |
| 9947767 | Self-limited inner spacer formation for gate-all-around field effect transistors | Robinhsinku Chao, Heng Wu, Chun Wing Yeung, Jingyun Zhang | 2018-04-17 |
| 9825122 | Multiple work function device using GeOx/TiN cap on work function setting metal | Takashi Ando, Pouya Hashemi | 2017-11-21 |
| 9773875 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Hemanth Jagannathan, Shogo Mochizuki, Koji Watanabe | 2017-09-26 |
| 9741822 | Simplified gate stack process to improve dual channel CMOS performance | Hemanth Jagannathan, Richard Southwick | 2017-08-22 |