Issued Patents All Time
Showing 726–750 of 767 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6989318 | Method for reducing shallow trench isolation consumption in semiconductor devices | Ying Li | 2006-01-24 |
| 6989323 | Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2006-01-24 |
| 6982196 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith | Michael P. Belyansky, Diane C. Boyd, Oleg Gluschenkov | 2006-01-03 |
| 6977194 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Dureseti Chidambarrao, Omer H. Dokumaci, Oleg Gluschenkov | 2005-12-20 |
| 6974981 | Isolation structures for imposing stress patterns | Dureseti Chidambarrao, Omer H. Dokumaci, Jack A. Mandelman | 2005-12-13 |
| 6946358 | Method of fabricating shallow trench isolation by ultra-thin SIMOX processing | Mark C. Hakey, Akihisa Sekiguchi | 2005-09-20 |
| 6939751 | Method and manufacture of thin silicon on insulator (SOI) with recessed channel | Huilong Zhu, Werner Rausch, Ying Zhang | 2005-09-06 |
| 6924517 | Thin channel FET with recessed source/drains and extensions | Huajie Chen, Philip J. Oldiges, Xinlin Wang, Huilong Zhu | 2005-08-02 |
| 6914303 | Ultra thin channel MOSFET | Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong, Omer H. Dokumaci | 2005-07-05 |
| 6911384 | Gate structure with independently tailored vertical doping profile | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-06-28 |
| 6911383 | Hybrid planar and finFET CMOS devices | Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub Kedzierski, Min Yang | 2005-06-28 |
| 6908850 | Structure and method for silicided metal gate transistors | Huilong Zhu | 2005-06-21 |
| 6905941 | Structure and method to fabricate ultra-thin Si channel devices | Thomas S. Kanarsky, Meikei Ieong, Wesley C. Natzle | 2005-06-14 |
| 6887798 | STI stress modification by nitrogen plasma treatment for improving performance in small width devices | Sadanand V. Deshpande, Werner Rausch, James A. Slinkman | 2005-05-03 |
| 6884667 | Field effect transistor with stressed channel and method for making same | Dureseti Chidambarrao, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis | 2005-04-26 |
| 6878582 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-04-12 |
| 6873010 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Omer H. Dokumaci, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-01-11 |
| 6838695 | CMOS device structure with improved PFET gate electrode | Ashima B. Chakravarti, Kevin K. Chan, Daniel A. Uriarte | 2005-01-04 |
| 6833569 | Self-aligned planar double-gate process by amorphization | Omer H. Dokumaci, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2004-12-21 |
| 6825529 | Stress inducing spacers | Dureseti Chidambarrao, Omer H. Dokumaci, Jack A. Mandelman, Xavier Baie | 2004-11-30 |
| 6812105 | Ultra-thin channel device with raised source and drain and solid source extension doping | Omer H. Dokumaci | 2004-11-02 |
| 6806534 | Damascene method for improved MOS transistor | Omer H. Dokumaci, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-10-19 |
| 6803315 | Method for blocking implants from the gate of an electronic device via planarizing films | Omer H. Dokumaci | 2004-10-12 |
| 6790733 | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer | Wesley C. Natzle, Sadanand V. Deshpande, Renee T. Mo, Patricia A. O'Neil | 2004-09-14 |