Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6548334 | Capping layer | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2003-04-15 |
| 6537866 | Method of forming narrow insulating spacers for use in reducing minimum component size | Jeffrey A. Shields, Jusuke Ogura, Bharath Rangarajan, Simon S. Chan | 2003-03-25 |
| 6509604 | Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation | Mark T. Ramsbey, Yu Sun, Chi Chang | 2003-01-21 |
| 6465835 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2002-10-15 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Narbeh Derhacobian, Janet Wang, Angela T. Hui, Ravi Sunkavalli +1 more | 2002-10-15 |
| 6455373 | Semiconductor device having gate edges protected from charge gain/loss | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun, Chi Chang | 2002-09-24 |
| 6448608 | Capping layer | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2002-09-10 |
| 6399984 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Chi Chang, Yu Sun, Jean Y. Yang | 2002-06-04 |
| 6369416 | Semiconductor device with contacts having a sloped profile | Angela T. Hui, Mark T. Ramsbey, Yu Sun | 2002-04-09 |
| 6355514 | Dual bit isolation scheme for flash devices | — | 2002-03-12 |
| 6342415 | Method and system for providing reduced-sized contacts in a semiconductor device | Angela T. Hui, Mark T. Ramsbey, Yu Sun | 2002-01-29 |
| 6337246 | Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing | Daniel Sobek, Timothy Thurgate, Carl Robert Huster, Mark T. Ramsbey, Sameer Haddad | 2002-01-08 |
| 6284600 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Chi Chang, Yu Sun, Jean Y. Yang | 2001-09-04 |
| 6274433 | Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices | Mark T. Ramsbey, Yu Sun, Kenneth Wo-Wai Au | 2001-08-14 |
| 6268624 | Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing | Daniel Sobek, Timothy Thurgate, Carl Robert Huster, Mark T. Ramsbey, Sameer Haddad | 2001-07-31 |
| 6261904 | Dual bit isolation scheme for flash devices | Bharath Rangarajan, Mike Templeton | 2001-07-17 |
| 6248627 | Method for protecting gate edges from charge gain/loss in semiconductor device | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun, Chi Chang | 2001-06-19 |
| 6242306 | Dual bit isolation scheme for flash memory devices having polysilicon floating gates | Angela T. Hui | 2001-06-05 |
| 6232630 | Light floating gate doping to improve tunnel oxide reliability | Mark T. Ramsbey, Yu Sun, Kenneth Wo-Wai Au, David Chi | 2001-05-15 |
| 6093650 | Method for fully planarized conductive line for a stack gate | Michael K. Templeton | 2000-07-25 |
| 6034394 | Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices | Mark T. Ramsbey, Yu Sun, Kenneth Wo-Wai Au | 2000-03-07 |
| 6034395 | Semiconductor device having a reduced height floating gate | Nicholas H. Tripsas, Effiong Ibok | 2000-03-07 |
| 6027998 | Method for fully planarized conductive line for a stack gate | Yowjuang W. Liu | 2000-02-22 |
| 5998301 | Method and system for providing tapered shallow trench isolation structure profile | Angela T. Hui, Kashmir Sahota | 1999-12-07 |
| 5966618 | Method of forming dual field isolation structures | Yu Sun, Mark T. Ramsbey, Chi Chang | 1999-10-12 |