Issued Patents All Time
Showing 51–75 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7541240 | Integration process flow for flash devices with low gap fill aspect ratio | Masaaki Higashitani | 2009-06-02 |
| 7504686 | Self-aligned non-volatile memory cell | Jeffrey W. Lutze, Henry Chien, George Matamis | 2009-03-17 |
| 7482223 | Multi-thickness dielectric for semiconductor memory | Masaaki Higashitani | 2009-01-27 |
| 7436019 | Non-volatile memory cells shaped to increase coupling to word lines | Jeffrey W. Lutze, Masaaki Higashitani | 2008-10-14 |
| 7436703 | Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices | Masaaki Higashitani, Hao Fang, Gerrit Jan Hemink | 2008-10-14 |
| 7365018 | Fabrication of semiconductor device for flash memory with increased select gate width | Masaaki Higashitani, Masayuki Ichige, Koji Hashimoto, Satoshi Tanaka, Kikuko Sugimae | 2008-04-29 |
| 7362615 | Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices | Masaaki Higashitani, Hao Fang, Gerrit Jan Hemink | 2008-04-22 |
| 7221008 | Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory | George Matamis, Henry Chien, Hao Fang | 2007-05-22 |
| 7202125 | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode | Masaaki Higashitani | 2007-04-10 |
| 7183153 | Method of manufacturing self aligned non-volatile memory cells | Jeffrey W. Lutze, Masaaki Higashitani | 2007-02-27 |
| 7105406 | Self aligned non-volatile memory cell and process for fabrication | Jeffrey W. Lutze, Henry Chien, George Matamis | 2006-09-12 |
| 7012008 | Dual spacer process for non-volatile memory devices | Jeffrey A. Shields, Mark T. Ramsbey, Yu Sun, Angela T. Hui, Maria C. Chan | 2006-03-14 |
| 6969654 | Flash NVROM devices with UV charge immunity | Mark T. Ramsbey, Jeffrey A. Shields, Angela T. Hui, Dawn Hopper | 2005-11-29 |
| 6934772 | Lowering display power consumption by dithering brightness | Vinh X. Bui | 2005-08-23 |
| 6867097 | Method of making a memory cell with polished insulator layer | Mark T. Ramsbey, Robert B. Ogle, Tommy Hsiao, Angela T. Hui, Marina V. Plat +1 more | 2005-03-15 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun, Chi Chang | 2004-10-26 |
| 6798002 | Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming | Robert B. Ogle, Mark T. Ramsbey | 2004-09-28 |
| 6787840 | Nitridated tunnel oxide barriers for flash memory technology circuitry | Mark T. Ramsbey, Yu Sun, Chi Chang | 2004-09-07 |
| 6713809 | Dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Kazuhiro Kurihara, Masaru Yano, Hideki Komori, Angela T. Hui | 2004-03-30 |
| 6689682 | Multilayer anti-reflective coating for semiconductor lithography | Robert B. Ogle, Marina V. Plat | 2004-02-10 |
| 6680507 | Dual bit isolation scheme for flash memory devices having polysilicon floating gates | Angela T. Hui | 2004-01-20 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation | Angela T. Hui, Richard J. Huang, Mark T. Ramsbey, Lu You | 2003-10-21 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Mark T. Ramsbey, Yu Sun, Chi Chang | 2003-08-12 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2003-07-08 |
| 6573140 | Process for making a dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Kiyoshi Izumi, Masaru Yano, Hideki Komori, Angela T. Hui | 2003-06-03 |