Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8258009 | Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof | Chih-Cheng Lee | 2012-09-04 |
| 8110931 | Wafer and semiconductor package | Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Jian-Cheng Chen, Wei Chi Yih +6 more | 2012-02-07 |
| 8076786 | Semiconductor package and method for packaging a semiconductor package | Chang Ying Hung, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Jian-Cheng Chen +1 more | 2011-12-13 |
| 8059422 | Thermally enhanced package structure | Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang +3 more | 2011-11-15 |
| 8053906 | Semiconductor package and method for processing and bonding a wire | Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Jian-Cheng Chen, Wei Chi Yih +3 more | 2011-11-08 |
| 8018075 | Semiconductor package, method for enhancing the bond of a bonding wire, and method for manufacturing a semiconductor package | Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Jian-Cheng Chen, Wei Chi Yih +1 more | 2011-09-13 |
| 7614888 | Flip chip package process | Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang +3 more | 2009-11-10 |
| 7581666 | Wire-bonding method for wire-bonding apparatus | Teck-Chong Lee, Chao-Fu Weng, Chian-Chi Lin, Chih-Nan Wei, Song-Fu Yang +2 more | 2009-09-01 |
| 7547575 | Two-stage die-bonding method for simultaneous die-bonding of multiple dies | Kao-Ming Su, Chao-Fu Weng, Teck-Chong Lee, Chian-Chi Lin, Chia-Jung Tsai +2 more | 2009-06-16 |
| 7445944 | Packaging substrate and manufacturing method thereof | Teck-Chong Lee, Chao-Fu Weng, Chian-Chi Lin, Che-Ya Chou, Shin-Hua Chao +2 more | 2008-11-04 |
| 7064428 | Wafer-level package structure | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +5 more | 2006-06-20 |
| 7041534 | Semiconductor chip package and method for making the same | Shin-Hua Chao, Jen-Kuang Fang | 2006-05-09 |
| 6989326 | Bump manufacturing method | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +2 more | 2006-01-24 |
| 6967153 | Bump fabrication process | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +5 more | 2005-11-22 |
| 6927964 | Structure for preventing burnt fuse pad from further electrical connection | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +5 more | 2005-08-09 |
| 6891360 | Plated probe structure | Brian S. Beaman, Keith E. Fogel, Paul A. Lauro, Eugene J. O'Sullivan, Da-Yuan Shih | 2005-05-10 |
| 6891274 | Under-bump-metallurgy layer for improving adhesion | William T. Chen, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang +1 more | 2005-05-10 |
| 6877653 | Method of modifying tin to lead ratio in tin-lead bump | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +5 more | 2005-04-12 |
| 6875683 | Method of forming bump | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +2 more | 2005-04-05 |
| 6864168 | Bump and fabricating process thereof | William T. Chen, Chun-Chi Lee, Su Tao, Chih-Huang Chang, Jeng-Da Wu +2 more | 2005-03-08 |
| 6861346 | Solder ball fabricating process | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +3 more | 2005-03-01 |
| 6846719 | Process for fabricating wafer bumps | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +5 more | 2005-01-25 |
| 6827252 | Bump manufacturing method | Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su +2 more | 2004-12-07 |
| 6819002 | Under-ball-metallurgy layer | William T. Chen, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang +1 more | 2004-11-16 |
| 6768332 | Semiconductor wafer and testing method for the same | Yueh-Lung Lin, Yao-Hsin Feng, Su Tao, Chi Cheng Pan, Kuo-Pin Yang +1 more | 2004-07-27 |