Issued Patents 2021
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205723 | Selective source/drain recess for improved performance, isolation, and scaling | Ardasheir Rahman, Junli Wang, Stuart A. Sieg, Christopher J. Waskiewicz | 2021-12-21 |
| 11195795 | Well-controlled edge-to-edge spacing between adjacent interconnects | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-12-07 |
| 11195792 | Top via stack | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2021-12-07 |
| 11189568 | Top via interconnect having a line with a reduced bottom dimension | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-11-30 |
| 11177132 | Self aligned block masks for implantation control | Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang | 2021-11-16 |
| 11177166 | Etch stop layer removal for capacitance reduction in damascene top via integration | Christopher J. Penny, Lawrence A. Clevenger, Robert R. Robison, Kisik Choi, Nicholas Anthony Lanzillo | 2021-11-16 |
| 11171084 | Top via with next level line selective growth | Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison | 2021-11-09 |
| 11164777 | Top via with damascene line and via | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2021-11-02 |
| 11158537 | Top vias with subtractive line formation | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-10-26 |
| 11152507 | Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance | Chen Zhang, Tenko Yamashita, Terence B. Hook | 2021-10-19 |
| 11145550 | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor | Junli Wang, Albert M. Young | 2021-10-12 |
| RE48616 | Isolation region fabrication for replacement gate processing | Edward J. Nowak | 2021-06-29 |
| 11031296 | 3D vertical FET with top and bottom gate contacts | Albert M. Chu | 2021-06-08 |
| 11024546 | Vertical field effect transistors | Edward J. Nowak | 2021-06-01 |
| 11011513 | Integrating a junction field effect transistor into a vertical field effect transistor | Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang | 2021-05-18 |
| 10991619 | Top via process accounting for misalignment by increasing reliability | Chen Zhang, Lawrence A. Clevenger, Benjamin D. Briggs, Chih-Chao Yang | 2021-04-27 |
| 10985257 | Vertical transport fin field effect transistor with asymmetric channel profile | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2021-04-20 |
| 10985073 | Vertical field effect transistor replacement metal gate fabrication | Ruilong Xie, Wenyu Xu, Zuoguang Liu | 2021-04-20 |
| 10978454 | Semiconductor device and method of forming the semiconductor device | Shawn P. Fetterolf, Terence B. Hook | 2021-04-13 |
| 10964812 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Terence B. Hook, Gauri Karve | 2021-03-30 |
| 10957696 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Ruqiang Bao, Dechao Guo, Vijay Narayanan | 2021-03-23 |
| 10957794 | Vertical transistor contact for cross-coupling in a memory cell | Terence B. Hook, Junli Wang | 2021-03-23 |
| 10943911 | Vertical transport devices with greater density through modified well shapes | Stuart A. Sieg, Junli Wang | 2021-03-09 |
| 10943992 | Transistor having straight bottom spacers | Kangguo Cheng, Christopher J. Waskiewicz, Michael P. Belyansky, Muthumanickam Sankarapandian, Puneet Harischandra Suvarna +1 more | 2021-03-09 |
| 10943831 | Vertical field effect transistors | Edward J. Nowak | 2021-03-09 |