Issued Patents 2017
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831324 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Chun Wing Yeung | 2017-11-28 |
| 9812556 | Semiconductor device and method of manufacturing the semiconductor device | Gen Tsutsui, Raghavasimhan Sreenivasan, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2017-11-07 |
| 9805989 | Sacrificial cap for forming semiconductor contact | Praneet Adusumilli, Zuoguang Liu, Jie Yang, Chun Wing Yeung | 2017-10-31 |
| 9799513 | Localized elastic strain relaxed buffer | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2017-10-24 |
| 9799765 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Junli Wang | 2017-10-24 |
| 9799736 | High acceptor level doping in silicon germanium | Mona A. Ebrish, Oleg Gluschenkov, Alexander Reznicek | 2017-10-24 |
| 9793272 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage | Dechao Guo, Andreas Scholze, Chun-Chen Yeh | 2017-10-17 |
| 9786661 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Dechao Guo, Andreas Scholze, Chun-Chen Yeh | 2017-10-10 |
| 9773901 | Bottom spacer formation for vertical transistor | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2017-09-26 |
| 9773875 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Hemanth Jagannathan, Choonghyun Lee, Koji Watanabe | 2017-09-26 |
| 9768104 | Method and structure to fabricate a nanoporous membrane | Zhenxing Bi, Kangguo Cheng, Hao Tang | 2017-09-19 |
| 9761499 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-09-12 |
| 9761609 | Structure having group III-V, Ge and SiGe Fins on insulator | Alexander Reznicek | 2017-09-12 |
| 9754968 | Structure and method to form III-V, Ge and SiGe fins on insulator | Alexander Reznicek | 2017-09-05 |
| 9754875 | Designable channel FinFET fuse | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2017-09-05 |
| 9748380 | Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure | Fee Li Lie, Junli Wang | 2017-08-29 |
| 9748359 | Vertical transistor bottom spacer formation | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2017-08-29 |
| 9748382 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2017-08-29 |
| 9735155 | Bulk silicon germanium FinFET | Kangguo Cheng, Juntao Li | 2017-08-15 |
| 9704990 | Vertical FET with strained channel | Junli Wang | 2017-07-11 |
| 9685553 | Generating tensile strain in bulk finFET channel | Yun-Yu Wang | 2017-06-20 |
| 9685384 | Devices and methods of forming epi for aggressive gate pitch | Ruilong Xie, Christopher M. Prindle, Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Pietro Montanini | 2017-06-20 |
| 9666493 | Semiconductor device structure with 110-PFET and 111-NFET curent flow direction | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-05-30 |
| 9666726 | Localized fin width scaling using a hydrogen anneal | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2017-05-30 |
| 9666486 | Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate | Mona A. Ebrish, Hemanth Jagannathan, Alexander Reznicek | 2017-05-30 |