Issued Patents 2017
Showing 1–25 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853001 | Prevention of reverse engineering of security chips | Qing Cao, Zhengwen Li, Fei Liu | 2017-12-26 |
| 9853056 | Strained CMOS on strain relaxation buffer substrate | Juntao Li, Balasubramanian Pranatharthiharan | 2017-12-26 |
| 9853131 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2017-12-26 |
| 9852982 | Anti-fuses with reduced programming voltages | Chengwen Pei, Juntao Li, Geng Wang | 2017-12-26 |
| 9853166 | Perfectly symmetric gate-all-around FET on suspended nanowire | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-12-26 |
| 9853132 | Nanosheet MOSFET with full-height air-gap spacer | Bruce B. Doris, Michael A. Guillorn, Xin Miao | 2017-12-26 |
| 9853054 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Juntao Li, Zuoguang Liu, Xin Miao | 2017-12-26 |
| 9853022 | MIM capacitor formation in RMG module | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-12-26 |
| 9853028 | Vertical FET with reduced parasitic capacitance | Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2017-12-26 |
| 9852917 | Methods of fabricating semiconductor fins by double sidewall image transfer patterning through localized oxidation enhancement of sacrificial mandrel sidewalls | — | 2017-12-26 |
| 9852951 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty | 2017-12-26 |
| 9847246 | Multiple finFET formation with epitaxy separation | Juntao Li, Geng Wang, Qintao Zhang | 2017-12-19 |
| 9847388 | High thermal budget compatible punch through stop integration using doped glass | Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh | 2017-12-19 |
| 9847259 | Germanium dual-fin field effect transistor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-12-19 |
| 9842835 | High density nanosheet diodes | Juntao Li, Geng Wang, Qintao Zhang | 2017-12-12 |
| 9842739 | Method and structure for enabling high aspect ratio sacrificial gates | Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan | 2017-12-12 |
| 9842929 | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-12-12 |
| 9837414 | Stacked complementary FETs featuring vertically stacked horizontal nanowires | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-12-05 |
| 9837415 | FinFET structures having silicon germanium and silicon fins with suppressed dopant diffusion | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-12-05 |
| 9837408 | Forming strained and unstrained features on a substrate | Zhenxing Bi, Peng Xu, Zheng Xu | 2017-12-05 |
| 9837410 | Fabrication of vertical field effect transistors with uniform structural profiles | — | 2017-12-05 |
| 9837407 | Semiconductor device with increased source/drain area | Chi-Chun Liu, Peng Xu, Jie Yang | 2017-12-05 |
| 9837440 | FinFET device with abrupt junctions | Hong He, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2017-12-05 |
| 9837403 | Asymmetrical vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2017-12-05 |
| 9837277 | Forming a contact for a tall fin transistor | Ruilong Xie, Tenko Yamashita | 2017-12-05 |