Issued Patents 2017
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852951 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2017-12-26 |
| 9853056 | Strained CMOS on strain relaxation buffer substrate | Kangguo Cheng, Juntao Li | 2017-12-26 |
| 9825044 | Method to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2017-11-21 |
| 9818873 | Forming stressed epitaxial layers between gates separated by different pitches | Emre Alptekin, Lars Liebmann, Injo Ok, Ravikumar Ramachandran, Soon-Cheon Seo +2 more | 2017-11-14 |
| 9812368 | Method to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2017-11-07 |
| 9806078 | FinFET spacer formation on gate sidewalls, between the channel and source/drain regions | Ruilong Xie, Christopher M. Prindle, Tenko Yamashita, Pietro Montanini, Soon-Cheon Seo | 2017-10-31 |
| 9799654 | FET trench dipole formation | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2017-10-24 |
| 9793378 | Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability | Nicolas Loubet, Shom Ponoth, Prasanna Khare, Qing Liu | 2017-10-17 |
| 9768173 | Semiconductor structure containing low-resistance source and drain contacts | Injo Ok, Charan V. Surisetty | 2017-09-19 |
| 9741823 | Fin cut during replacement gate formation | Andrew M. Greene, Sivananda K. Kanakasabapathy, John R. Sporre | 2017-08-22 |
| 9741715 | Structure to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2017-08-22 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy +6 more | 2017-08-01 |
| 9721834 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2017-08-01 |
| 9704760 | Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2017-07-11 |
| 9704753 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2017-07-11 |
| 9698101 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Charan V. V. S. Surisetty, Ruilong Xie | 2017-07-04 |
| 9691765 | Fin type field effect transistors with different pitches and substantially uniform fin reveal | Zhenxing Bi, Kangguo Cheng, Thamarai S. Devarajan | 2017-06-27 |
| 9685340 | Stable contact on one-sided gate tie-down structure | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-20 |
| 9685384 | Devices and methods of forming epi for aggressive gate pitch | Ruilong Xie, Christopher M. Prindle, Soon-Cheon Seo, Pietro Montanini, Shogo Mochizuki | 2017-06-20 |
| 9685530 | Replacement metal gate dielectric cap | Damon B. Farmer, Michael A. Guillorn, George S. Tulevski | 2017-06-20 |
| 9673190 | ESD device compatible with bulk bias capability | Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber +1 more | 2017-06-06 |
| 9673101 | Minimize middle-of-line contact line shorts | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-06 |
| 9660028 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2017-05-23 |
| 9646885 | Method to prevent lateral epitaxial growth in semiconductor devices by performing plasma nitridation process on Fin ends | Hui Zang | 2017-05-09 |
| 9634110 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Ruilong Xie | 2017-04-25 |