Issued Patents 2017
Showing 1–25 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853158 | Method and structure for multigate FinFet device epi-extension junction control by hydrogen treatment | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-12-26 |
| 9853115 | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts | Hiroaki Niimi, Shariq Siddiqui | 2017-12-26 |
| 9853151 | Fully silicided linerless middle-of-line (MOL) contact | Joshua M. Rubin | 2017-12-26 |
| 9853117 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Hui Zang | 2017-12-26 |
| 9853159 | Self aligned epitaxial based punch through control | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-12-26 |
| 9837277 | Forming a contact for a tall fin transistor | Kangguo Cheng, Ruilong Xie | 2017-12-05 |
| 9831241 | Method and structure for improving finFET with epitaxy source/drain | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-11-28 |
| 9818823 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Ruilong Xie | 2017-11-14 |
| 9812443 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-11-07 |
| 9806155 | Split fin field effect transistor enabling back bias on fin type field effect transistors | Veeraraghavan S. Basker, Zuoguang Liu, Xin Miao | 2017-10-31 |
| 9806078 | FinFET spacer formation on gate sidewalls, between the channel and source/drain regions | Ruilong Xie, Christopher M. Prindle, Balasubramanian Pranatharthiharan, Pietro Montanini, Soon-Cheon Seo | 2017-10-31 |
| 9806153 | Controlling channel length for vertical FETs | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-10-31 |
| 9805973 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2017-10-31 |
| 9799746 | Preventing leakage inside air-gap spacer during contact formation | Kangguo Cheng, Ruilong Xie | 2017-10-24 |
| 9793157 | Etch stop for airgap protection | Kangguo Cheng, Ruilong Xie | 2017-10-17 |
| 9786737 | FinFET with reduced parasitic capacitance | Kangguo Cheng, Darsen D. Lu, Xin Miao | 2017-10-10 |
| 9786546 | Bulk to silicon on insulator device | Terence B. Hook, Joshua M. Rubin | 2017-10-10 |
| 9780185 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Hui Zang | 2017-10-03 |
| 9773881 | Etch stop for airgap protection | Kangguo Cheng, Ruilong Xie | 2017-09-26 |
| 9773709 | Forming CMOSFET structures with different contact liners | Kangguo Cheng, Zuoguang Liu | 2017-09-26 |
| 9768272 | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity | Pouya Hashemi, Hong He, Alexander Reznicek | 2017-09-19 |
| 9768027 | FinFET having controlled dielectric region height | Dechao Guo, Zuoguang Liu, Chun-Chen Yeh | 2017-09-19 |
| 9761498 | Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs | Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin | 2017-09-12 |
| 9761721 | Field effect transistors with self-aligned extension portions of epitaxial active regions | Effendi Leobandung | 2017-09-12 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2017-08-22 |