Issued Patents 2017
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853116 | Partial sacrificial dummy gate with CMOS device with high-k metal gate | Wilfried E. Haensch, Shu-Jen Han, Daniel Jaeger, Yu Lu, Keith Kwong Hon Wong | 2017-12-26 |
| 9793272 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage | Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh | 2017-10-17 |
| 9786661 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh | 2017-10-10 |
| 9773893 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Sivananda K. Kanakasabapathy, Peng Xu | 2017-09-26 |
| 9768027 | FinFET having controlled dielectric region height | Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2017-09-19 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Andrew M. Greene, Sivananda K. Kanakasabapathy, Gauri Karve +6 more | 2017-08-01 |
| 9704754 | Self-aligned spacer for cut-last transistor fabrication | Ruqiang Bao, Zuoguang Liu | 2017-07-11 |
| 9647169 | Light emitting diode (LED) using carbon materials | Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan | 2017-05-09 |
| 9570466 | Structure and method to form passive devices in ETSOI process flow | Ming Cai, Chun-Chen Yeh | 2017-02-14 |