| 9818746 |
Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate |
Unoh Kwon, Kai Zhao |
2017-11-14 |
| 9799656 |
Semiconductor device having a gate stack with tunable work function |
Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan |
2017-10-24 |
| 9768171 |
Method to form dual tin layers as pFET work metal stack |
Siddarth A. Krishnan |
2017-09-19 |
| 9704754 |
Self-aligned spacer for cut-last transistor fabrication |
Dechao Guo, Zuoguang Liu |
2017-07-11 |
| 9704758 |
Forming a semiconductor structure for reduced negative bias temperature instability |
Siddarth A. Krishnan |
2017-07-11 |
| 9691655 |
Etch stop in a dep-etch-dep process |
Keith Kwong Hon Wong |
2017-06-27 |
| 9589806 |
Integrated circuit with replacement gate stacks and method of forming same |
Unoh Kwon, Huihang Dong, John A. Fitzsimmons |
2017-03-07 |
| 9583400 |
Gate stack with tunable work function |
Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan |
2017-02-28 |
| 9576958 |
Forming a semiconductor structure for reduced negative bias temperature instability |
Siddarth A. Krishnan |
2017-02-21 |
| 9559016 |
Semiconductor device having a gate stack with tunable work function |
Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan |
2017-01-31 |
| 9553092 |
Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs |
Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong |
2017-01-24 |