Issued Patents 2017
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853158 | Method and structure for multigate FinFet device epi-extension junction control by hydrogen treatment | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-12-26 |
| 9853159 | Self aligned epitaxial based punch through control | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-12-26 |
| 9847388 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2017-12-19 |
| 9812443 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-11-07 |
| 9805973 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-10-31 |
| 9806153 | Controlling channel length for vertical FETs | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-10-31 |
| 9793171 | Buried source-drain contact for integrated circuit transistor devices and method of making same | Qing Liu, Ruilong Xie, Xiuyu Cai, William J. Taylor, Jr. | 2017-10-17 |
| 9793272 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage | Dechao Guo, Shogo Mochizuki, Andreas Scholze | 2017-10-17 |
| 9793395 | Vertical vacuum channel transistor | Qing Liu, Ruilong Xie | 2017-10-17 |
| 9786661 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Dechao Guo, Shogo Mochizuki, Andreas Scholze | 2017-10-10 |
| 9773885 | Self aligned gate shape preventing void formation | Andrew M. Greene, Qing Liu, Ruilong Xie | 2017-09-26 |
| 9768027 | FinFET having controlled dielectric region height | Dechao Guo, Zuoguang Liu, Tenko Yamashita | 2017-09-19 |
| 9761717 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Kangguo Cheng, Juntao Li | 2017-09-12 |
| 9755031 | Trench epitaxial growth for a FinFET device having reduced capacitance | Qing Liu, Xiuyu Cai, Ruilong Xie | 2017-09-05 |
| 9748351 | Process for integrated circuit fabrication including a uniform depth tungsten recess technique | Qing Liu, Ruilong Xie | 2017-08-29 |
| 9748352 | Multi-channel gate-all-around FET | Qing Liu, Ruilong Xie, Xiuyu Cai | 2017-08-29 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-08-22 |
| 9728419 | Fin density control of multigate devices through sidewall image transfer processes | Hong He, Chiahsun Tseng, Yunpeng Yin | 2017-08-08 |
| 9728534 | Densely spaced fins for semiconductor fin field effect transistors | Hong He, Chiahsun Tseng, Yunpeng Yin | 2017-08-08 |
| 9716170 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-07-25 |
| 9716160 | Extended contact area using undercut silicide extensions | Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita | 2017-07-25 |
| 9711618 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-07-18 |
| 9711645 | Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2017-07-18 |
| 9691763 | Multi-gate FinFET semiconductor device with flexible design width | Veeraraghavan S. Basker, Tenko Yamashita | 2017-06-27 |
| 9685555 | High-reliability, low-resistance contacts for nanoscale transistors | Qing Liu, Nicolas Loubet, Ruilong Xie, Xiuyu Cai | 2017-06-20 |