Issued Patents 2017
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818873 | Forming stressed epitaxial layers between gates separated by different pitches | Emre Alptekin, Lars Liebmann, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo +2 more | 2017-11-14 |
| 9799654 | FET trench dipole formation | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-10-24 |
| 9768173 | Semiconductor structure containing low-resistance source and drain contacts | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2017-09-19 |
| 9728462 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2017-08-08 |
| 9704760 | Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-07-11 |
| 9698101 | Self-aligned local interconnect technology | Andrew M. Greene, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie | 2017-07-04 |
| 9685340 | Stable contact on one-sided gate tie-down structure | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-20 |
| 9673101 | Minimize middle-of-line contact line shorts | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-06-06 |
| 9627382 | CMOS NFET and PFET comparable spacer width | Kangguo Cheng, Soon-Cheon Seo | 2017-04-18 |
| 9627322 | Semiconductor device having reduced contact resistance | Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2017-04-18 |
| 9595592 | Forming dual contact silicide using metal multi-layer and ion beam mixing | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-03-14 |
| 9583584 | Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods | Chanro Park | 2017-02-28 |
| 9564370 | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling | Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2017-02-07 |
| 9536791 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Su Chen Fan, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2017-01-03 |