Issued Patents 2017
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847390 | Self-aligned wrap-around contacts for nanosheet devices | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-12-19 |
| 9847418 | Methods of forming fin cut regions by oxidizing fin portions | Kwan-Yong Lim, Min Gyu Sung | 2017-12-19 |
| 9837404 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Hoon Kim, Ruilong Xie, Kwan-Yong Lim | 2017-12-05 |
| 9831132 | Methods for forming fin structures | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2017-11-28 |
| 9824920 | Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices | Ruilong Xie, Hoon Kim, Min Gyu Sung | 2017-11-21 |
| 9818836 | Gate cut method for replacement metal gate integration | Min Gyu Sung, Ruilong Xie, Dong-Ick Lee | 2017-11-14 |
| 9799748 | Method of forming inner spacers on a nano-sheet/wire device | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-10-24 |
| 9780208 | Method and structure of forming self-aligned RMG gate for VFET | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-10-03 |
| 9780197 | Method of controlling VFET channel length | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-10-03 |
| 9761495 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Ruilong Xie, Min Gyu Sung, Catherine B. Labelle, Hoon Kim | 2017-09-12 |
| 9741623 | Dual liner CMOS integration methods for FinFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim | 2017-08-22 |
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Hoon Kim, Min Gyu Sung, Ruilong Xie | 2017-08-15 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Min Gyu Sung, Ruilong Xie, Hoon Kim | 2017-08-15 |
| 9735063 | Methods for forming fin structures | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-08-15 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim, Sukwon Hong | 2017-08-01 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2017-06-27 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Hoon Kim, Min Gyu Sung, Ruilong Xie | 2017-06-20 |
| 9653356 | Methods of forming self-aligned device level contact structures | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-05-16 |
| 9646884 | Block level patterning process | Sukwon Hong, Hoon Kim, Min Gyu Sung | 2017-05-09 |
| 9634115 | Methods of forming a protection layer on a semiconductor device and the resulting device | Ruilong Xie, Xiuyu Cai | 2017-04-25 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Hoon Kim, Min Gyu Sung | 2017-04-18 |
| 9601387 | Method of making threshold voltage tuning using self-aligned contact cap | Xiuyu Cai, Hoon Kim | 2017-03-21 |
| 9589850 | Method for controlled recessing of materials in cavities in IC devices | Kisup Chung, Sivananda K. Kanakasabapathy | 2017-03-07 |
| 9583584 | Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods | Injo Ok | 2017-02-28 |