Issued Patents 2017
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847390 | Self-aligned wrap-around contacts for nanosheet devices | Ruilong Xie, Chanro Park, Min Gyu Sung | 2017-12-19 |
| 9837404 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Chanro Park, Ruilong Xie, Kwan-Yong Lim | 2017-12-05 |
| 9831132 | Methods for forming fin structures | Chanro Park, Min Gyu Sung, Ruilong Xie | 2017-11-28 |
| 9824920 | Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices | Chanro Park, Ruilong Xie, Min Gyu Sung | 2017-11-21 |
| 9799748 | Method of forming inner spacers on a nano-sheet/wire device | Ruilong Xie, Min Gyu Sung, Chanro Park | 2017-10-24 |
| 9780197 | Method of controlling VFET channel length | Ruilong Xie, Min Gyu Sung, Chanro Park | 2017-10-03 |
| 9780208 | Method and structure of forming self-aligned RMG gate for VFET | Ruilong Xie, Chanro Park, Min Gyu Sung | 2017-10-03 |
| 9761495 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Ruilong Xie, Min Gyu Sung, Catherine B. Labelle, Chanro Park | 2017-09-12 |
| 9741623 | Dual liner CMOS integration methods for FinFET devices | Min Gyu Sung, Chanro Park, Ruilong Xie | 2017-08-22 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Min Gyu Sung, Ruilong Xie, Chanro Park | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Chanro Park, Min Gyu Sung | 2017-08-15 |
| 9735063 | Methods for forming fin structures | Chanro Park, Min Gyu Sung, Ruilong Xie | 2017-08-15 |
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Min Gyu Sung, Ruilong Xie, Chanro Park | 2017-08-15 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Ruilong Xie, Chanro Park, Sukwon Hong | 2017-08-01 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Min Gyu Sung, Chanro Park, Ruilong Xie | 2017-06-27 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Min Gyu Sung, Ruilong Xie, Chanro Park | 2017-06-20 |
| 9682827 | Conveyor apparatus | Min Sung Kim, Tae Gon Kim, Hyun-Joon Park, Seung-Yong Oh, Hyun-Hee Lee | 2017-06-20 |
| 9680981 | Home appliance and control method thereof | Si-Hyun Park, Talipov Elmurod, Dal Young Yu, Young Woon Kim, Jae Seok Lee +1 more | 2017-06-13 |
| 9666690 | Integrated circuit and method for fabricating the same having a replacement gate structure | Kisik Choi | 2017-05-30 |
| 9653356 | Methods of forming self-aligned device level contact structures | Chanro Park, Ruilong Xie, Min Gyu Sung | 2017-05-16 |
| 9646884 | Block level patterning process | Chanro Park, Sukwon Hong, Min Gyu Sung | 2017-05-09 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Chanro Park, Min Gyu Sung | 2017-04-18 |
| 9607904 | Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices | Albert S. Lee, Paul R. Besser, Kisik Choi, Edward Haywood, Salil Mujumdar | 2017-03-28 |
| 9601387 | Method of making threshold voltage tuning using self-aligned contact cap | Xiuyu Cai, Chanro Park | 2017-03-21 |
| 9603152 | Wireless network channel allocation method for interference avoidance | Tae Sik Nam | 2017-03-21 |