Issued Patents 2017
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847390 | Self-aligned wrap-around contacts for nanosheet devices | Ruilong Xie, Chanro Park, Hoon Kim | 2017-12-19 |
| 9847418 | Methods of forming fin cut regions by oxidizing fin portions | Kwan-Yong Lim, Chanro Park | 2017-12-19 |
| 9837404 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim | 2017-12-05 |
| 9831132 | Methods for forming fin structures | Chanro Park, Hoon Kim, Ruilong Xie | 2017-11-28 |
| 9824920 | Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices | Chanro Park, Ruilong Xie, Hoon Kim | 2017-11-21 |
| 9818836 | Gate cut method for replacement metal gate integration | Ruilong Xie, Chanro Park, Dong-Ick Lee | 2017-11-14 |
| 9799748 | Method of forming inner spacers on a nano-sheet/wire device | Ruilong Xie, Chanro Park, Hoon Kim | 2017-10-24 |
| 9780208 | Method and structure of forming self-aligned RMG gate for VFET | Ruilong Xie, Chanro Park, Hoon Kim | 2017-10-03 |
| 9780197 | Method of controlling VFET channel length | Ruilong Xie, Chanro Park, Hoon Kim | 2017-10-03 |
| 9779987 | Titanium silicide formation in a narrow source-drain contact | Kwanyong LIM, Hiroaki Niimi | 2017-10-03 |
| 9779960 | Hybrid fin cutting processes for FinFET semiconductor devices | Ruilong Xie, Catherine B. Labelle | 2017-10-03 |
| 9761495 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Ruilong Xie, Catherine B. Labelle, Chanro Park, Hoon Kim | 2017-09-12 |
| 9741623 | Dual liner CMOS integration methods for FinFET devices | Chanro Park, Ruilong Xie, Hoon Kim | 2017-08-22 |
| 9735063 | Methods for forming fin structures | Chanro Park, Hoon Kim, Ruilong Xie | 2017-08-15 |
| 9732315 | Axenic inoculation system for microalgae using TR tube of triiodide resin and method for culturing axenic culture | Jong-Hee KWON, Ji Won YANG, Ju-Young Jung, Gi Bok Nam, Min Sung Park +1 more | 2017-08-15 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Ruilong Xie, Chanro Park, Hoon Kim | 2017-08-15 |
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Hoon Kim, Ruilong Xie, Chanro Park | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Chanro Park, Hoon Kim | 2017-08-15 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Ruilong Xie, Hoon Kim, Chanro Park, Sukwon Hong | 2017-08-01 |
| 9722024 | Formation of semiconductor structures employing selective removal of fins | Ruilong Xie, Catherine B. Labelle | 2017-08-01 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Chanro Park, Hoon Kim, Ruilong Xie | 2017-06-27 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Hoon Kim, Ruilong Xie, Chanro Park | 2017-06-20 |
| 9653356 | Methods of forming self-aligned device level contact structures | Chanro Park, Ruilong Xie, Hoon Kim | 2017-05-16 |
| 9646884 | Block level patterning process | Chanro Park, Sukwon Hong, Hoon Kim | 2017-05-09 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Hoon Kim, Chanro Park | 2017-04-18 |