Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847418 | Methods of forming fin cut regions by oxidizing fin portions | Min Gyu Sung, Chanro Park | 2017-12-19 |
| 9842933 | Formation of bottom junction in vertical FET devices | Hiroaki Niimi, Steven Bentley, Daniel Chanemougame | 2017-12-12 |
| 9837404 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie | 2017-12-05 |
| 9812452 | Method to form silicide and contact at embedded epitaxial facet | James Walter Blatchford, Shashank S. Ekbote, Younsung Choi | 2017-11-07 |
| 9799751 | Methods of forming a gate structure on a vertical transistor device | John H. Zhang, Steven Bentley | 2017-10-24 |
| 9773708 | Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI | John H. Zhang, Steven Bentley | 2017-09-26 |
| 9761662 | Active area shapes reducing device size | Bipul C. Paul | 2017-09-12 |
| 9711511 | Vertical channel transistor-based semiconductor memory structure | Ryan Ryoung-Han Kim, Motoi Ichihashi, Youngtag Woo, Deepak Nayak | 2017-07-18 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | Steven Bentley, John H. Zhang, Hiroaki Niimi | 2017-05-02 |
| 9640533 | Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression | Christopher M. Prindle | 2017-05-02 |
| 9543215 | Punch-through-stop after partial fin etch | Steven Bentley, Chanro Park | 2017-01-10 |
| 9536793 | Self-aligned gate-first VFETs using a gate spacer recess | John H. Zhang, Steven Bentley, Chanro Park | 2017-01-03 |