Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9786607 | Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer | Sukwon Hong, William J. Taylor, Jr. | 2017-10-10 |
| 9735054 | Gate tie-down enablement with inner spacer | Andre P. Labonte, Lars Liebmann, Sanjay C. Mehta | 2017-08-15 |
| 9728462 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita | 2017-08-08 |
| 9728456 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Sukwon Hong, William J. Taylor, Jr. | 2017-08-08 |
| 9653571 | Freestanding spacer having sub-lithographic lateral dimension and method of forming same | Hsueh-Chung Chen, Dong-Kwon Kim, Sean Lian, Fee Li Lie, Linus Jang | 2017-05-16 |
| 9627257 | Gate tie-down enablement with inner spacer | Andre P. Labonte, Lars Liebmann, Sanjay C. Mehta | 2017-04-18 |
| 9583442 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Sukwon Hong, William J. Taylor, Jr. | 2017-02-28 |
| 9576901 | Contact area structure and method for manufacturing the same | Hsueh-Chung Chen, Chih-Chao Yang | 2017-02-21 |
| 9570573 | Self-aligned gate tie-down contacts with selective etch stop liner | Lars Liebmann, Ruilong Xie | 2017-02-14 |
| 9570397 | Local interconnect structure including non-eroded contact via trenches | Vimal Kamineni, Andre P. Labonte, Ruilong Xie | 2017-02-14 |
| 9536791 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita | 2017-01-03 |