FL

Fee Li Lie

IBM: 34 patents #58 of 10,852Top 1%
Globalfoundries: 3 patents #173 of 1,311Top 15%
Samsung: 1 patents #6,542 of 15,326Top 45%
Overall (2017): #460 of 506,227Top 1%
35
Patents 2017

Issued Patents 2017

Showing 25 most recent of 35 patents

Patent #TitleCo-InventorsDate
9853127 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Brent A. Anderson, Huiming Bu, Terence B. Hook, Junli Wang 2017-12-26
9842931 Self-aligned shallow trench isolation and doping for vertical fin transistors Brent A. Anderson, Junli Wang 2017-12-12
9842739 Method and structure for enabling high aspect ratio sacrificial gates Kangguo Cheng, Ryan O. Jung, Jeffrey C. Shearer, John R. Sporre, Sean Teehan 2017-12-12
9842737 Self-aligned quadruple patterning process Matthew E. Colburn, Sivananda K. Kanakasabapathy, Stuart A. Sieg 2017-12-12
9812324 Methods to control fin tip placement Lei Zhuang, Lars Liebmann, Stuart A. Sieg, Mahender Kumar, Shreesh Narasimha +3 more 2017-11-07
9805935 Bottom source/drain silicidation for vertical field-effect transistor (FET) Brent A. Anderson, Huiming Bu, Terence B. Hook, Junli Wang 2017-10-31
9805992 Strained finFET device fabrication Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Stuart A. Sieg 2017-10-31
9805991 Strained finFET device fabrication Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Stuart A. Sieg 2017-10-31
9799765 Formation of a bottom source-drain for vertical field-effect transistors Marc A. Bergendahl, Kangguo Cheng, Shogo Mochizuki, Junli Wang 2017-10-24
9793402 Retaining strain in finFET devices Bruce B. Doris, Gauri Karve, Junli Wang 2017-10-17
9786666 Method to form dual channel semiconductor material fins Kangguo Cheng, Ryan O. Jung, Eric R. Miller, John R. Sporre, Sean Teehan 2017-10-10
9754798 Hybridization fin reveal for uniform fin reveal depth across different fin pitches Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Peng Xu 2017-09-05
9755071 Merged gate for vertical transistors Brent A. Anderson, Edward J. Nowak, Junli Wang 2017-09-05
9754942 Single spacer for complementary metal oxide semiconductor process flow Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Eric R. Miller, Jeffrey C. Shearer +2 more 2017-09-05
9748146 Single spacer for complementary metal oxide semiconductor process flow Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Eric R. Miller, Jeffrey C. Shearer +2 more 2017-08-29
9748380 Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure Shogo Mochizuki, Junli Wang 2017-08-29
9741856 Stress retention in fins of fin field-effect transistors Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Stuart A. Sieg, John R. Sporre 2017-08-22
9728642 Retaining strain in finFET devices Bruce B. Doris, Gauri Karve, Junli Wang 2017-08-08
9728622 Dummy gate formation using spacer pull down hardmask Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan 2017-08-08
9716184 Enabling large feature alignment marks with sidewall image transfer patterning Kangguo Cheng, Sivananda K. Kanakasabapathy, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more 2017-07-25
9711507 Separate N and P fin etching for reduced CMOS device leakage Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve +3 more 2017-07-18
9704859 Forming semiconductor fins with self-aligned patterning Kangguo Cheng, Peng Xu 2017-07-11
9659779 Method and structure for enabling high aspect ratio sacrificial gates Kangguo Cheng, Ryan O. Jung, Jeffrey C. Shearer, John R. Sporre, Sean Teehan 2017-05-23
9653571 Freestanding spacer having sub-lithographic lateral dimension and method of forming same Hsueh-Chung Chen, Su Chen Fan, Dong-Kwon Kim, Sean Lian, Linus Jang 2017-05-16
9640640 FinFET device with channel strain Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve 2017-05-02