Issued Patents 2017
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853127 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang | 2017-12-26 |
| 9847416 | Performance-enhanced vertical device and method of forming thereof | Edward J. Nowak, Robert R. Robison | 2017-12-19 |
| 9842931 | Self-aligned shallow trench isolation and doping for vertical fin transistors | Fee Li Lie, Junli Wang | 2017-12-12 |
| 9805935 | Bottom source/drain silicidation for vertical field-effect transistor (FET) | Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang | 2017-10-31 |
| 9793374 | Vertical transistor fabrication and devices | Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla | 2017-10-17 |
| 9786656 | Integration of bipolar transistor into complimentary metal-oxide-semiconductor process | Xuefeng Liu, Junli Wang | 2017-10-10 |
| 9786788 | Vertical-transport FinFET device with variable Fin pitch | Edward J. Nowak | 2017-10-10 |
| 9786765 | FINFET having notched fins and method of forming same | Edward J. Nowak, Andreas Scholze | 2017-10-10 |
| 9786751 | Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s) | Jeffrey B. Johnson, Edward J. Nowak | 2017-10-10 |
| 9786507 | Methods of forming field effect transistors using a gate cut process following final gate formation | Edward J. Nowak | 2017-10-10 |
| 9768304 | Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the semiconductor fin | Andres Bryant, Edward J. Nowak | 2017-09-19 |
| 9761712 | Vertical transistors with merged active area regions | Albert M. Chu, Terence B. Hook, Seong-Dong Kim | 2017-09-12 |
| 9755071 | Merged gate for vertical transistors | Fee Li Lie, Edward J. Nowak, Junli Wang | 2017-09-05 |
| 9748271 | Hybrid circuit including a tunnel field-effect transistor | Tamilmani Ethirajan, Edward J. Nowak | 2017-08-29 |
| RE46448 | Isolation region fabrication for replacement gate processing | Edward J. Nowak | 2017-06-20 |
| 9680473 | Ultra dense vertical transport FET circuits | Albert M. Chu, Edward J. Nowak | 2017-06-13 |
| 9673199 | Gate cutting for a vertical transistor device | Sivananda K. Kanakasabapathy, Stuart A. Sieg, John R. Sporre, Junli Wang | 2017-06-06 |
| 9673055 | Method for quadruple frequency FinFETs with single-fin removal | Andres Bryant, Edward J. Nowak | 2017-06-06 |
| 9666578 | Vertical FETs with high density capacitor | — | 2017-05-30 |
| 9659941 | Integrated circuit structure with methods of electrically connecting same | Edward J. Nowak | 2017-05-23 |
| 9653360 | Vertical field effect transistors | Edward J. Nowak | 2017-05-16 |
| 9613861 | Damascene wires with top via structures | Edward J. Nowak | 2017-04-04 |
| 9613955 | Hybrid circuit including a tunnel field-effect transistor | Tamilmani Ethirajan, Edward J. Nowak | 2017-04-04 |
| 9595524 | FinFET source-drain merged by silicide-based material | Nicolas L. Breil, Christian Lavoie | 2017-03-14 |
| 9583489 | Solid state diffusion doping for bulk finFET devices | Hemanth Jagannathan, Sanjay C. Mehta, Balasubramanian Pranatharthiharan | 2017-02-28 |