Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842737 | Self-aligned quadruple patterning process | Matthew E. Colburn, Sivananda K. Kanakasabapathy, Fee Li Lie | 2017-12-12 |
| 9812324 | Methods to control fin tip placement | Lei Zhuang, Lars Liebmann, Fee Li Lie, Mahender Kumar, Shreesh Narasimha +3 more | 2017-11-07 |
| 9805991 | Strained finFET device fabrication | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie | 2017-10-31 |
| 9805992 | Strained finFET device fabrication | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie | 2017-10-31 |
| 9741856 | Stress retention in fins of fin field-effect transistors | Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, John R. Sporre | 2017-08-22 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy +6 more | 2017-08-01 |
| 9673199 | Gate cutting for a vertical transistor device | Brent A. Anderson, Sivananda K. Kanakasabapathy, John R. Sporre, Junli Wang | 2017-06-06 |
| 9589958 | Pitch scalable active area patterning structure and process for multi-channel finFET technologies | Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller | 2017-03-07 |