Issued Patents 2017
Showing 25 most recent of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853127 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie | 2017-12-26 |
| 9853022 | MIM capacitor formation in RMG module | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-12-26 |
| 9847261 | Metal reflow for middle of line contacts | Juntao Li, Chih-Chao Yang | 2017-12-19 |
| 9842931 | Self-aligned shallow trench isolation and doping for vertical fin transistors | Brent A. Anderson, Fee Li Lie | 2017-12-12 |
| 9837309 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2017-12-05 |
| 9837535 | Directional deposition of protection layer | Hong He, Juntao Li, Chih-Chao Yang | 2017-12-05 |
| 9818650 | Extra gate device for nanosheet | Bruce B. Doris, Terence B. Hook | 2017-11-14 |
| 9812567 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-11-07 |
| 9805987 | Self-aligned punch through stopper liner for bulk FinFET | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-10-31 |
| 9805935 | Bottom source/drain silicidation for vertical field-effect transistor (FET) | Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie | 2017-10-31 |
| 9799765 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki | 2017-10-24 |
| 9793402 | Retaining strain in finFET devices | Bruce B. Doris, Gauri Karve, Fee Li Lie | 2017-10-17 |
| 9793175 | FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-10-17 |
| 9786563 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-10-10 |
| 9786656 | Integration of bipolar transistor into complimentary metal-oxide-semiconductor process | Brent A. Anderson, Xuefeng Liu | 2017-10-10 |
| 9780091 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-10-03 |
| 9768079 | Extra gate device for nanosheet | Bruce B. Doris, Terence B. Hook | 2017-09-19 |
| 9768118 | Contact having self-aligned air gap spacers | Juntao Li, Chih-Chao Yang | 2017-09-19 |
| 9761496 | Field effect transistor contacts | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-09-12 |
| 9761500 | FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-09-12 |
| 9761699 | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures | Bruce B. Doris, Hong He, Nicolas Loubet | 2017-09-12 |
| 9755071 | Merged gate for vertical transistors | Brent A. Anderson, Fee Li Lie, Edward J. Nowak | 2017-09-05 |
| 9748380 | Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure | Fee Li Lie, Shogo Mochizuki | 2017-08-29 |
| 9741577 | Metal reflow for middle of line contacts | Juntao Li, Chih-Chao Yang | 2017-08-22 |
| 9741792 | Bulk nanosheet with dielectric isolation | Kangguo Cheng, Bruce B. Doris | 2017-08-22 |