| 9837309 |
Semiconductor via structure with lower electrical resistance |
Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang |
2017-12-05 |
| 9831182 |
Multiple pre-clean processes for interconnect fabrication |
Wei Wang, Chih-Chao Yang |
2017-11-28 |
| 9799552 |
Low resistance metal contacts to interconnects |
Stephen M. Gates, Gregory M. Fritz, Eric A. Joseph |
2017-10-24 |
| 9786550 |
Low resistance metal contacts to interconnects |
Stephen M. Gates, Gregory M. Fritz, Eric A. Joseph |
2017-10-10 |
| 9786603 |
Surface nitridation in metal interconnects |
Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang |
2017-10-10 |
| 9768113 |
Self aligned via in integrated circuit |
Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Douglas M. Trickett +1 more |
2017-09-19 |
| 9658523 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +1 more |
2017-05-23 |
| 9659820 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +2 more |
2017-05-23 |
| 9548243 |
Self aligned via and pillar cut for at least a self aligned double pitch |
Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert |
2017-01-17 |
