| 9786551 |
Trench structure for high performance interconnection lines of different resistivity and method of making same |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu |
2017-10-10 |
| 9709898 |
Amplification method for photoresist exposure in semiconductor chip manufacturing |
Daniel A. Corliss |
2017-07-18 |
| 9691900 |
Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch |
Kangguo Cheng, Ali Khakifirooz |
2017-06-27 |
| 9680015 |
Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch |
Kangguo Cheng, Ali Khakifirooz |
2017-06-13 |
| 9659820 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Akil Khamisi Sutton +2 more |
2017-05-23 |
| 9658523 |
Interconnect structure having large self-aligned vias |
John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Terry A. Spooner +1 more |
2017-05-23 |
| 9627533 |
High selectivity nitride removal process based on selective polymer deposition |
Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura |
2017-04-18 |
| 9577068 |
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation |
Gregory Costrini, Ravikumar Ramachandran, Reinaldo Vega |
2017-02-21 |
