Issued Patents 2017
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837394 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2017-12-05 |
| 9786551 | Trench structure for high performance interconnection lines of different resistivity and method of making same | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise | 2017-10-10 |
| 9755030 | Method for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2017-09-05 |
| 9741613 | Method for producing self-aligned line end vias and related device | John H. Zhang, Lawrence A. Clevenger | 2017-08-22 |
| 9659818 | Forming self-aligned dual patterning mandrel and non-mandrel interconnects | Lawrence A. Clevenger, John H. Zhang | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise, Terry A. Spooner +1 more | 2017-05-23 |
| 9659820 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise, Akil Khamisi Sutton +2 more | 2017-05-23 |
| 9660105 | Finfet crosspoint flash memory | Ramachandra Divakaruni, Arvind Kumar | 2017-05-23 |
| 9646939 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier | 2017-05-09 |
| 9640765 | Carbon nanotube device | Lawrence A. Clevenger, Chandrasekhar Narayan, Gregory A. Northrop, Brian C. Sapp | 2017-05-02 |
| 9640552 | Multi-height fin field effect transistors | Pranita Kerber, Sudesh Saroop | 2017-05-02 |
| 9633986 | Technique for fabrication of microelectronic capacitors and resistors | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Edem Wornyo | 2017-04-25 |
| 9607893 | Method of forming self-aligned metal lines and vias | John H. Zhang, Lawrence A. Clevenger | 2017-03-28 |
| 9601570 | Structure for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2017-03-21 |