Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818623 | Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit | Jason E. Stephens, Guillaume Bouche, Craig Child | 2017-11-14 |
| 9812396 | Interconnect structure for semiconductor devices with multiple power rails and redundancy | Jason E. Stephens, Guillaume Bouche, Shreesh Narasimha, Patrick R. Justison, Craig Child | 2017-11-07 |
| 9786545 | Method of forming ANA regions in an integrated circuit | Guillaume Bouche, Jason E. Stephens, Craig Child, Shreesh Narasimha | 2017-10-10 |
| 9646939 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Walter Kleemeier | 2017-05-09 |