Issued Patents 2017
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852984 | Cut first alternative for 2D self-aligned via | Andy Wei, Sudharshanan Raghunathan | 2017-12-26 |
| 9852986 | Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit | Jason E. Stephens | 2017-12-26 |
| 9825031 | Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices | Andy Wei, Jason E. Stephens, David Permana, Jagannathan Vasudevan | 2017-11-21 |
| 9818641 | Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines | Jason E. Stephens | 2017-11-14 |
| 9818623 | Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit | Jason E. Stephens, Byoung Youp Kim, Craig Child | 2017-11-14 |
| 9818640 | Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines | Jason E. Stephens | 2017-11-14 |
| 9818876 | Method for fabricating a finFET metallization architecture using a self-aligned contact etch | — | 2017-11-14 |
| 9818651 | Methods, apparatus and system for a passthrough-based architecture | Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason E. Stephens +3 more | 2017-11-14 |
| 9812351 | Interconnection cells having variable width metal lines and fully-self aligned continuity cuts | Nicholas V. LiCausi, Lars Liebmann | 2017-11-07 |
| 9812400 | Contact line having insulating spacer therein and method of forming same | Veeraraghavan S. Basker, Keith H. Tabakman, Patrick Carpenter, Michael V. Aquilino | 2017-11-07 |
| 9812396 | Interconnect structure for semiconductor devices with multiple power rails and redundancy | Jason E. Stephens, Shreesh Narasimha, Patrick R. Justison, Byoung Youp Kim, Craig Child | 2017-11-07 |
| 9812324 | Methods to control fin tip placement | Lei Zhuang, Lars Liebmann, Stuart A. Sieg, Fee Li Lie, Mahender Kumar +3 more | 2017-11-07 |
| 9805988 | Method of forming semiconductor structure including suspended semiconductor layer and resulting structure | Steven Bentley | 2017-10-31 |
| 9793169 | Methods for forming mask layers using a flowable carbon-containing silicon dioxide material | Huy Cao, Huang Liu, Songkram Srivathanakul | 2017-10-17 |
| 9786545 | Method of forming ANA regions in an integrated circuit | Jason E. Stephens, Byoung Youp Kim, Craig Child, Shreesh Narasimha | 2017-10-10 |
| 9779943 | Compensating for lithographic limitations in fabricating semiconductor interconnect structures | Jason E. Stephens | 2017-10-03 |
| 9691775 | Combined SADP fins for semiconductor devices and methods of making the same | Nicholas V. LiCausi, Eric S. Kozarsky | 2017-06-27 |
| 9691626 | Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions | Jason E. Stephens | 2017-06-27 |
| 9679805 | Self-aligned back end of line cut | Andy Wei, Mark A. Zaleski | 2017-06-13 |
| 9679809 | Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines | Jongwook Kye, Yan Wang, Chenchen Jacob Wang, Wenhui Wang, Lei Yuan +1 more | 2017-06-13 |
| 9673316 | Vertical semiconductor device having frontside interconnections | Christopher S. Blair, Albert Bergemont, Sudarsan Uppili, Fanling H. Yang | 2017-06-06 |
| 9666488 | Pass-through contact using silicide | Tuhin Guha Neogi, David Pritchard, Scott Luning, David Doman | 2017-05-30 |
| 9660075 | Integrated circuits with dual silicide contacts and methods for fabricating same | Shao-Ming Koh, Jeremy A. Wahl, Andy Wei | 2017-05-23 |
| 9660040 | Transistor contacts self-aligned two dimensions | Andy Wei, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye +1 more | 2017-05-23 |
| 9640625 | Self-aligned gate contact formation | Andy Wei, Gabriel Padron Wells, Andre P. Labonte, Jing Wan | 2017-05-02 |