Issued Patents 2017
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9786666 | Method to form dual channel semiconductor material fins | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, John R. Sporre, Sean Teehan | 2017-10-10 |
| 9754942 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Jeffrey C. Shearer +2 more | 2017-09-05 |
| 9748146 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Jeffrey C. Shearer +2 more | 2017-08-29 |
| 9728622 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2017-08-08 |
| 9716184 | Enabling large feature alignment marks with sidewall image transfer patterning | Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-07-25 |
| 9627277 | Method and structure for enabling controlled spacer RIE | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-04-18 |
| 9620590 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2017-04-11 |
| 9608065 | Air gap spacer for metal gates | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2017-03-28 |
| 9589958 | Pitch scalable active area patterning structure and process for multi-channel finFET technologies | Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg | 2017-03-07 |
| 9536744 | Enabling large feature alignment marks with sidewall image transfer patterning | Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-01-03 |