Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852946 | Self aligned conductive lines | Sean D. Burns, Lawrence A. Clevenger, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2017-12-26 |
| 9842737 | Self-aligned quadruple patterning process | Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg | 2017-12-12 |
| 9779944 | Method and structure for cut material selection | Sean D. Burns, Lawrence A. Clevenger, Nelson Felix, Sivananda K. Kanakasabapathy, Yann Mignot +3 more | 2017-10-03 |
| 9773700 | Aligning conductive vias with trenches | Sean D. Burns, Lawrence A. Clevenger, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2017-09-26 |
| 9659824 | Graphoepitaxy directed self-assembly process for semiconductor fin formation | Joy Cheng, Michael A. Guillorn, Chi-Chun Liu, Melia Tjio, HsinYu Tsai | 2017-05-23 |
| 9607886 | Self aligned conductive lines with relaxed overlay | Sean D. Burns, Lawrence A. Clevenger, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2017-03-28 |
| 9601345 | Fin trimming in a double sit process | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2017-03-21 |
| 9563122 | Method to harden photoresist for directed self-assembly processes | Joy Cheng, Chi-Chun Liu | 2017-02-07 |