Issued Patents 2017
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853132 | Nanosheet MOSFET with full-height air-gap spacer | Kangguo Cheng, Bruce B. Doris, Xin Miao | 2017-12-26 |
| 9852260 | Method and recording medium of reducing chemoepitaxy directed self-assembled defects | Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, HsinYu Tsai | 2017-12-26 |
| 9831324 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Chi-Chun Liu, Shogo Mochizuki, Chun Wing Yeung | 2017-11-28 |
| 9812321 | Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure | Bruce B. Doris, Isaac Lauer, Xin Miao | 2017-11-07 |
| 9786597 | Self-aligned pitch split for unidirectional metal wiring | Josephine B. Chang, Eric A. Joseph, Hiroyuki Miyazoe | 2017-10-10 |
| 9755017 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Isaac Lauer, Nicolas Loubet | 2017-09-05 |
| 9754965 | Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2017-09-05 |
| 9748404 | Method for fabricating a semiconductor device including gate-to-bulk substrate isolation | Josephine B. Chang, Isaac Lauer, Xin Miao | 2017-08-29 |
| 9738765 | Hybrid topographical and chemical pre-patterns for directed self-assembly of block copolymers | Markus Brink, Joy Cheng, Gregory S. Doerk, Alexander Friz, Chi-Chun Liu +4 more | 2017-08-22 |
| 9728542 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-08 |
| 9721888 | Trench silicide with self-aligned contact vias | Josephine B. Chang, Fei Liu, Adam M. Pyzyna | 2017-08-01 |
| 9716036 | Electronic device including moat power metallization in trench | Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Adam M. Pyzyna | 2017-07-25 |
| 9691615 | Chemoepitaxy-based directed self assembly process with tone inversion for unidirectional wiring | Markus Brink, Joy Cheng, Gregory S. Doerk, HsinYu Tsai | 2017-06-27 |
| 9685530 | Replacement metal gate dielectric cap | Damon B. Farmer, Balasubramanian Pranatharthiharan, George S. Tulevski | 2017-06-20 |
| 9684753 | Techniques for generating nanowire pad data from pre-existing design data | Karthik Balakrishnan, Josephine B. Chang, Jeffrey W. Sleight | 2017-06-20 |
| 9659824 | Graphoepitaxy directed self-assembly process for semiconductor fin formation | Joy Cheng, Matthew E. Colburn, Chi-Chun Liu, Melia Tjio, HsinYu Tsai | 2017-05-23 |
| 9653547 | Integrated etch stop for capped gate and method for manufacturing the same | Josephine B. Chang, Bruce B. Doris, Isaac Lauer, Xin Miao | 2017-05-16 |
| 9647139 | Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer | Bruce B. Doris, Isaac Lauer, Xin Miao | 2017-05-09 |
| 9646883 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Chung-Hsun Lin, HsinYu Tsai | 2017-05-09 |
| 9620622 | Replacement metal gate dielectric cap | Damon B. Farmer, Balasubramanian Pranatharthiharan, George S. Tulevski | 2017-04-11 |
| 9581899 | 2-dimensional patterning employing tone inverted graphoepitaxy | Kafai Lai, Jed W. Pitera, HsinYu Tsai | 2017-02-28 |
| 9582631 | Method and system for template pattern optimization for DSA patterning using graphoepitaxy | Kafai Lai, Melih Ozlem, HsinYu Tsai | 2017-02-28 |
| 9576817 | Pattern decomposition for directed self assembly patterns templated by sidewall image transfer | Joy Cheng, Chi-Chun Liu, HsinYu Tsai | 2017-02-21 |
| 9570550 | Stacked nanowire semiconductor device | William L. Nicoll, Hanfei Wang | 2017-02-14 |
| 9564502 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2017-02-07 |