Issued Patents 2017
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627322 | Semiconductor device having reduced contact resistance | Injo Ok, Charan V. Surisetty | 2017-04-18 |
| 9620622 | Replacement metal gate dielectric cap | Damon B. Farmer, Michael A. Guillorn, George S. Tulevski | 2017-04-11 |
| 9614047 | Gate contact with vertical isolation from source-drain | David V. Horak, Shom Ponoth, Ruilong Xie | 2017-04-04 |
| 9595578 | Undercut insulating regions for silicon-on-insulator device | Kangguo Cheng, Bruce B. Doris, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2017-03-14 |
| 9595592 | Forming dual contact silicide using metal multi-layer and ion beam mixing | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2017-03-14 |
| 9590074 | Method to prevent lateral epitaxial growth in semiconductor devices | Hui Zang | 2017-03-07 |
| 9583489 | Solid state diffusion doping for bulk finFET devices | Brent A. Anderson, Hemanth Jagannathan, Sanjay C. Mehta | 2017-02-28 |
| 9576961 | Semiconductor devices with sidewall spacers of equal thickness | Kangguo Cheng, Soon-Cheon Seo | 2017-02-21 |
| 9576957 | Self-aligned source/drain contacts | Praneet Adusumilli, Emre Alptekin, Kangguo Cheng, Shom Ponoth | 2017-02-21 |
| 9576954 | POC process flow for conformal recess fill | Andrew M. Greene, Sanjay C. Mehta, Ruilong Xie | 2017-02-21 |
| 9570555 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2017-02-14 |
| 9564370 | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling | Injo Ok, Sanjay C. Mehta, Soon-Cheon Seo, Charan V. Surisetty | 2017-02-07 |
| 9564372 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2017-02-07 |
| 9558995 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2017-01-31 |
| 9536988 | Parasitic capacitance reduction | Junli Wang | 2017-01-03 |