Issued Patents 2017
Showing 26–50 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837405 | Fabrication of a vertical fin field effect transistor having a consistent channel width | Juntao Li | 2017-12-05 |
| 9837403 | Asymmetrical vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2017-12-05 |
| 9837509 | Semiconductor device including strained finFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-12-05 |
| 9831241 | Method and structure for improving finFET with epitaxy source/drain | Ali Khakifirooz, Alexander Reznicek, Tenko Yamashita | 2017-11-28 |
| 9824934 | Shallow trench isolation recess process flow for vertical field effect transistor fabrication | Zhenxing Bi, Bruce Miao, Xin Miao | 2017-11-21 |
| 9825174 | FinFET with dielectric isolated channel | Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2017-11-21 |
| 9818877 | Embedded source/drain structure for tall finFET and method of formation | Veeraraghavan S. Basker, Ali Khakifirooz, Henry K. Utomo, Reinaldo Vega | 2017-11-14 |
| 9818823 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Xin Miao, Ruilong Xie, Tenko Yamashita | 2017-11-14 |
| 9818647 | Germanium dual-fin field effect transistor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-11-14 |
| 9818741 | Structure and method to prevent EPI short between trenches in FINFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim +5 more | 2017-11-14 |
| 9818875 | Approach to minimization of strain loss in strained fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2017-11-14 |
| 9812553 | Unipolar spacer formation for finFETs | Peng Xu, Jie Yang | 2017-11-07 |
| 9812567 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-11-07 |
| 9812575 | Contact formation for stacked FinFETs | Alexander Reznicek, Pouya Hashemi, Dominic J. Schepis | 2017-11-07 |
| 9812443 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-11-07 |
| 9812357 | Self-limiting silicide in highly scaled fin technology | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-11-07 |
| 9812394 | Faceted structure formed by self-limiting etch | Ali Khakifirooz, Juntao Li, Werner Rausch | 2017-11-07 |
| 9806084 | Anti-fuse with reduced programming voltage | Juntao Li, Chengwen Pei, Geng Wang | 2017-10-31 |
| 9805983 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Hao Tang, Peng Xu | 2017-10-31 |
| 9806153 | Controlling channel length for vertical FETs | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-10-31 |
| 9805987 | Self-aligned punch through stopper liner for bulk FinFET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-10-31 |
| 9806173 | Channel-last replacement metal-gate vertical field effect transistor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-10-31 |
| 9799749 | Vertical transport FET devices with uniform bottom spacer | Zhenxing Bi, Juntao Li, Xin Miao | 2017-10-24 |
| 9799655 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2017-10-24 |
| 9799730 | FINFETs with high quality source/drain structures | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-10-24 |