Issued Patents 2017
Showing 76–100 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9786563 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-10-10 |
| 9786547 | Channel silicon germanium formation method | Nicolas Degors, Shawn P. Fetterolf, Ahmet S. Ozcan | 2017-10-10 |
| 9780091 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-10-03 |
| 9780088 | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-10-03 |
| 9780173 | High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-10-03 |
| 9780194 | Vertical transistor structure with reduced parasitic gate capacitance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-10-03 |
| 9779995 | Highly scaled tunnel FET with tight pitch and method to fabricate same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-10-03 |
| 9773913 | Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-26 |
| 9773907 | Method to controllably etch silicon recess for ultra shallow junctions | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-09-26 |
| 9773870 | Strained semiconductor device | Peng Xu | 2017-09-26 |
| 9773867 | FinFET semiconductor devices with replacement gate structures | Ruilong Xie, Xiuyu Cai, Ali Khakifirooz | 2017-09-26 |
| 9773881 | Etch stop for airgap protection | Ruilong Xie, Tenko Yamashita | 2017-09-26 |
| 9773709 | Forming CMOSFET structures with different contact liners | Zuoguang Liu, Tenko Yamashita | 2017-09-26 |
| 9773783 | Forming metal-insulator-metal capacitor | Veeraraghavan S. Basker | 2017-09-26 |
| 9773780 | Devices including gates with multiple lengths | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-26 |
| 9773893 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2017-09-26 |
| 9773905 | Strained FinFET by epitaxial stressor independent of gate pitch | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-09-26 |
| 9768085 | Top contact resistance measurement in vertical FETs | Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang | 2017-09-19 |
| 9768104 | Method and structure to fabricate a nanoporous membrane | Zhenxing Bi, Shogo Mochizuki, Hao Tang | 2017-09-19 |
| 9768166 | Integrated LDMOS and VFET transistors | Juntao Li, Geng Wang, Qintao Zhang | 2017-09-19 |
| 9768072 | Fabrication of a vertical fin field effect transistor with reduced dimensional variations | — | 2017-09-19 |
| 9768075 | Method and structure to enable dual channel fin critical dimension control | Marc A. Bergendahl, John R. Sporre, Sean Teehan | 2017-09-19 |
| 9761450 | Forming a fin cut in a hardmask | Zhenxing Bi, Juntao Li, Peng Xu | 2017-09-12 |
| 9761717 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Juntao Li, Chun-Chen Yeh | 2017-09-12 |
| 9761726 | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-12 |