Issued Patents 2017
Showing 101–125 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761728 | Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same | Xin Miao, Wenyu Xu, Chen Zhang | 2017-09-12 |
| 9761726 | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-12 |
| 9761610 | Strain release in PFET regions | Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-09-12 |
| 9761667 | Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-09-12 |
| 9761694 | Vertical FET with selective atomic layer deposition gate | Xin Miao, Wenyu Xu, Chen Zhang | 2017-09-12 |
| 9761587 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-12 |
| 9761717 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Juntao Li, Chun-Chen Yeh | 2017-09-12 |
| 9755073 | Fabrication of vertical field effect transistor structure with strained channels | Juntao Li | 2017-09-05 |
| 9754941 | Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2017-09-05 |
| 9754942 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Jessica Dechene, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +2 more | 2017-09-05 |
| 9754933 | Large area diode co-integrated with vertical field-effect-transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-09-05 |
| 9753006 | High density nano-array for sensing | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2017-09-05 |
| 9748146 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Jessica Dechene, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer +2 more | 2017-08-29 |
| 9748239 | Fin-double-gated junction field effect transistor | Tak H. Ning | 2017-08-29 |
| 9748381 | Pillar formation for heat dissipation and isolation in vertical field effect transistors | Zhenxing Bi, Peng Xu, Chen Zhang | 2017-08-29 |
| 9748385 | Method for forming vertical Schottky contact FET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-29 |
| 9748245 | Multiple finFET formation with epitaxy separation | Juntao Li, Peng Xu | 2017-08-29 |
| 9748336 | Semiconductor device including dual-layer source/drain region | Robert H. Dennard, Zhen Zhang | 2017-08-29 |
| 9748365 | SiGe and Si FinFET structures and methods for making the same | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-08-29 |
| 9748114 | Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance | Subramanian S. Iyer, Pranita Kerber, Ali Khakifirooz | 2017-08-29 |
| 9741672 | Preventing unauthorized use of integrated circuits for radiation-hard applications | Bruce B. Doris, Ali Khakifirooz, Kenneth P. Rodbell | 2017-08-22 |
| 9741626 | Vertical transistor with uniform bottom spacer formed by selective oxidation | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-08-22 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-08-22 |
| 9741609 | Middle of line cobalt interconnection | Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John H. Zhang | 2017-08-22 |
| 9741792 | Bulk nanosheet with dielectric isolation | Bruce B. Doris, Junli Wang | 2017-08-22 |