Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9792251 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2017-10-17 |
| 9748114 | Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance | Kangguo Cheng, Pranita Kerber, Ali Khakifirooz | 2017-08-29 |
| 9690927 | Providing an authenticating service of a chip | Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt | 2017-06-27 |
| 9588937 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2017-03-07 |
| 9543229 | Combination of TSV and back side wiring in 3D integration | Pooja R. Batra, John W. Golz, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-10 |
| 9536809 | Combination of TSV and back side wiring in 3D integration | Pooja R. Batra, John W. Golz, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-03 |