Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852006 | Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-12-26 |
| 9797946 | Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2017-10-24 |
| 9792251 | Array of processor core circuits with reversible tiers | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-10-17 |
| 9747545 | Self-timed, event-driven neurosynaptic core controller | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-08-29 |
| 9588937 | Array of processor core circuits with reversible tiers | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-03-07 |
| 9563841 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2017-02-07 |