| 9852006 |
Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits |
Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more |
2017-12-26 |
| 9818058 |
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation |
Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more |
2017-11-14 |
| 9797946 |
Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more |
2017-10-24 |
| 9792251 |
Array of processor core circuits with reversible tiers |
Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2017-10-17 |
| 9747545 |
Self-timed, event-driven neurosynaptic core controller |
Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more |
2017-08-29 |
| 9588937 |
Array of processor core circuits with reversible tiers |
Rodrigo Alvarez-Icaza Rivera, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more |
2017-03-07 |
| 9563841 |
Globally asynchronous and locally synchronous (GALS) neuromorphic network |
Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha |
2017-02-07 |
| 9558443 |
Dual deterministic and stochastic neurosynaptic core circuit |
Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more |
2017-01-31 |
