Issued Patents 2017
Showing 151–175 of 370 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9721885 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2017-08-01 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy, Gauri Karve +6 more | 2017-08-01 |
| 9721897 | Transistor with air spacer and self-aligned contact | Xin Miao, Peng Xu, Chen Zhang | 2017-08-01 |
| 9721970 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9721845 | Vertical field effect transistors with bottom contact metal directly beneath fins | Xin Miao, Wenyu Xu, Chen Zhang | 2017-08-01 |
| 9722043 | Self-aligned trench silicide process for preventing gate contact to silicide shorts | Veeraraghavan S. Basker | 2017-08-01 |
| 9716064 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2017-07-25 |
| 9716086 | Method and structure for forming buried ESD with FinFETs | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9716142 | Stacked nanowires | Zhenxing Bi, Juntao Li, Xin Miao | 2017-07-25 |
| 9716145 | Strained stacked nanowire field-effect transistors (FETs) | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9716170 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-07-25 |
| 9716184 | Enabling large feature alignment marks with sidewall image transfer patterning | Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-07-25 |
| 9716045 | Directly forming SiGe fins on oxide | Hong He, Juntao Li, Junli Wang | 2017-07-25 |
| 9716046 | Method and structure for forming dielectric isolated finFET with improved source/drain epitaxy | Juntao Li | 2017-07-25 |
| 9716042 | Fin field-effect transistor (FinFET) with reduced parasitic capacitance | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-07-25 |
| 9716155 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9716158 | Air gap spacer between contact and gate region | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9711618 | Fabrication of vertical field effect transistor structure with controlled gate length | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-07-18 |
| 9704993 | Method of preventing epitaxy creeping under the spacer | Veeraraghavan S. Basker, Ali Khakifirooz, Sreenivasan Raghavasimhan | 2017-07-11 |
| 9704859 | Forming semiconductor fins with self-aligned patterning | Fee Li Lie, Peng Xu | 2017-07-11 |
| 9704863 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2017-07-11 |
| 9704991 | Gate height and spacer uniformity | Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John H. Zhang | 2017-07-11 |
| 9701532 | Multi-faced component-based electromechanical device | Qing Cao, Zhengwen Li, Fei Liu | 2017-07-11 |
| 9704753 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty | 2017-07-11 |
| 9704856 | On-chip MIM capacitor | Peng Xu | 2017-07-11 |