Issued Patents 2017
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818909 | LED light extraction enhancement enabled using self-assembled particles patterned surface | Jeehwan Kim, Ning Li, Devendra K. Sadana | 2017-11-14 |
| 9799747 | Low resistance contact for semiconductor devices | Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-10-24 |
| 9799600 | Nickel-silicon fuse for FinFET structures | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-10-24 |
| 9793114 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Bruce B. Doris, Alexander Reznicek | 2017-10-17 |
| 9768254 | Leakage-free implantation-free ETSOI transistors | Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana | 2017-09-19 |
| 9768262 | Embedded carbon-doped germanium as stressor for germanium nFET devices | Jeffrey L. Dittmar, Sebastian Naczas, Alexander Reznicek, Devendra K. Sadana | 2017-09-19 |
| 9754875 | Designable channel FinFET fuse | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2017-09-05 |
| 9748353 | Method of making a gallium nitride device | Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2017-08-29 |
| 9741880 | Three-dimensional conductive electrode for solar cell | Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana | 2017-08-22 |
| 9741807 | FinFET device with vertical silicide on recessed source/drain epitaxy regions | Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2017-08-22 |
| 9722033 | Doped zinc oxide as n+ layer for semiconductor devices | Joel P. Desouza, Jeehwan Kim, Ko-Tao Lee, Devendra K. Sadana | 2017-08-01 |
| 9722039 | Fabricating high-power devices | Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2017-08-01 |
| 9716207 | Low reflection electrode for photovoltaic devices | Jeehwan Kim, David B. Mitzi, Mark T. Winkler | 2017-07-25 |
| 9713250 | Patterned metallization handle layer for controlled spalling | Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Paul A. Lauro, Devendra K. Sadana | 2017-07-18 |
| 9704860 | Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation | Karthik Balakrishnan, Sivananda K. Kanakasabapathy, Alexander Reznicek | 2017-07-11 |
| 9666674 | Formation of large scale single crystalline graphene | Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park | 2017-05-30 |
| 9660116 | Nanowires formed by employing solder nanodots | Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu | 2017-05-23 |
| 9653570 | Junction interlayer dielectric for reducing leakage current in semiconductor devices | Joel P. de Souza, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-05-16 |
| 9646832 | Porous fin as compliant medium to form dislocation-free heteroepitaxial films | Kangguo Cheng, Jeehwan Kim, Devendra K. Sadana | 2017-05-09 |
| 9634164 | Reduced light degradation due to low power deposition of buffer layer | Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana | 2017-04-25 |
| 9620592 | Doped zinc oxide and n-doping to reduce junction leakage | Joel P. de Souza, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-04-11 |
| 9601482 | Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication | Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty | 2017-03-21 |
| 9601624 | SOI based FINFET with strained source-drain regions | Stephen W. Bedell, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2017-03-21 |
| 9583572 | FinFET devices having silicon germanium channel fin structures with uniform thickness | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2017-02-28 |
| 9576806 | FinFET device with vertical silicide on recessed source/drain epitaxy regions | Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2017-02-21 |